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DAC5682ZIRGC25 Datasheet(PDF) 2 Page - Texas Instruments |
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DAC5682ZIRGC25 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 59 page CLKIN CLKINC DCLKP 1.2V Reference EXTIO EXTLO BIASJ IOUTB1 IOUTB2 16bit DAC Clock Multiplying PLL 2x-32x D0P D0N D15P D15N DCLKN SYNCP SYNCN IOUTA1 IOUTA2 16bit DAC Delay Lock Loop (DLL) FIFO Sync Disable Sync & Control x2 x2 x2 16 DLL Control x2 FIR0 Mode Control DACA_gain DACB_gain 4 4 SYNC=’0->1' (transition) 16 PLL Control Clock Distribution FDAC FDAC/2 PLL Bypass 2 PLL Enable 16 B A 13 A-Offset 13 FIR1 (x2 Bypass) (x1 Bypass) TXEnable=’1' FDAC/4 SW_Sync 2 2 47t 76dB HBF 47t 76dB HBF 47t 76dB HBF 47t 76dB HBF 16 Sync Disable DAC5682Z SLLS853C – AUGUST 2007 – REVISED JUNE 2009 ........................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5682Z |
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