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CC430F5135IRGZ Datasheet(PDF) 70 Page - Texas Instruments

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Part No. CC430F5135IRGZ
Description  MSP430 SoC with RF Core
Download  118 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CC430F5135IRGZ Datasheet(HTML) 70 Page - Texas Instruments

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D – MAY 2009 – REVISED JULY 2010
www.ti.com
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
2
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
2
mA
tCPT
Cumulative program time(1)
16
ms
Program/erase endurance
104
105
cycles
tRetention
Data retention duration
TJ = 25°C
100
years
tWord
Word or byte program time(2)
64
85
µs
tBlock, 0
Block program time for first byte or word(2)
49
65
µs
Block program time for each additional byte or word, except for last
tBlock, 1–(N–1)
37
49
µs
byte or word(2)
tBlock, N
Block program time for last byte or word(2)
55
73
µs
Erase time for segment erase, mass erase, and bank erase when
tErase
23
32
ms
available(2)
MCLK frequency in marginal read mode
fMCLK,MGR
0
1
MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1)
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2)
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW, En
2.2 V/3 V
1
µs
edge)(1)
tSBW,Rst
Spy-Bi-Wire return to normal operation time
15
100
µs
2.2 V
0
5
MHz
fTCK
TCK input frequency - 4-wire JTAG(2)
3 V
0
10
MHz
Rinternal
Internal pull-down resistance on TEST
2.2 V/3 V
45
60
80
k
Ω
(1)
Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2)
fTCK may be restricted to meet the timing requirements of the module selected.
70
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Copyright © 2009–2010, Texas Instruments Incorporated


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