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CC430F5135IRGZ Datasheet(PDF) 60 Page - Texas Instruments

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Part No. CC430F5135IRGZ
Description  MSP430 SoC with RF Core
Download  118 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CC430F5135IRGZ Datasheet(HTML) 60 Page - Texas Instruments

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D – MAY 2009 – REVISED JULY 2010
www.ti.com
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1), Figure 17 and Figure 18)
PMMCOR
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EVx
1.8 V
11
0
ns
3.0 V
8
tSTE,LEAD
STE lead time, STE low to clock
2.4 V
7
3
3.0 V
6
1.8 V
3
0
ns
3.0 V
3
STE lag time, Last clock to STE
tSTE,LAG
high
2.4 V
3
3
3.0 V
3
1.8 V
66
0
ns
3.0 V
50
STE access time, STE low to
tSTE,ACC
SOMI data out
2.4 V
36
3
3.0 V
30
1.8 V
30
0
ns
3.0 V
23
STE disable time, STE high to
tSTE,DIS
SOMI high impedance
2.4 V
16
3
3.0 V
13
1.8 V
5
0
ns
3.0 V
5
tSU,SI
SIMO input data setup time
2.4 V
2
3
ns
3.0 V
2
1.8 V
5
0
ns
3.0 V
5
tHD,SI
SIMO input data hold time
2.4 V
5
3
ns
3.0 V
5
1.8 V
76
0
ns
3.0 V
60
UCLK edge to SOMI valid,
tVALID,SO
SOMI output data valid time(2)
CL = 20 pF
2.4 V
44
3
ns
3.0 V
40
1.8 V
18
0
ns
3.0 V
12
tHD,SO
SOMI output data hold time(3)
CL = 20 pF
2.4 V
10
3
ns
3.0 V
8
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached master.
(2)
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3)
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 15
and Figure 16.
60
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Copyright © 2009–2010, Texas Instruments Incorporated


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