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CC430F5135IRGZ Datasheet(PDF) 58 Page - Texas Instruments

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Part No. CC430F5135IRGZ
Description  MSP430 SoC with RF Core
Download  118 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CC430F5135IRGZ Datasheet(HTML) 58 Page - Texas Instruments

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D – MAY 2009 – REVISED JULY 2010
www.ti.com
USCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fUSCI
USCI input clock frequency
External: UCLK
fSYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK
1
MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
2.2 V
50
600
tt
UART receive deglitch time(1)
ns
3 V
50
600
(1)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50% ± 10%
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1), Figure 15 and Figure 16)
PMMCOR
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
EVx
1.8 V
55
0
ns
3.0 V
38
tSU,MI
SOMI input data setup time
2.4 V
30
3
ns
3.0 V
25
1.8 V
0
0
ns
3.0 V
0
tHD,MI
SOMI input data hold time
2.4 V
0
3
ns
3.0 V
0
1.8 V
20
0
ns
3.0 V
18
UCLK edge to SIMO valid,
tVALID,MO
SIMO output data valid time(2)
CL = 20 pF
2.4 V
16
3
ns
3.0 V
15
1.8 V
-10
0
ns
3.0 V
-8
tHD,MO
SIMO output data hold time(3)
CL = 20 pF
2.4 V
-10
3
ns
3.0 V
-8
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3)
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 15 and Figure 16.
58
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Copyright © 2009–2010, Texas Instruments Incorporated


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