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CC430F5135IRGZ Datasheet(PDF) 56 Page - Texas Instruments

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Part No. CC430F5135IRGZ
Description  MSP430 SoC with RF Core
Download  118 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CC430F5135IRGZ Datasheet(HTML) 56 Page - Texas Instruments

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D – MAY 2009 – REVISED JULY 2010
www.ti.com
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SVSLE = 0, PMMCOREV = 2
0
nA
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
µA
SVSLE = 1, dVCORE/dt = 10 mV/µs,
2.5
SVSLFP = 1
tpd(SVSL)
SVSL propagation delay
µs
SVSLE = 1, dVCORE/dt = 1 mV/µs,
20
SVSLFP = 0
SVSLE = 0
→ 1, dVCORE/dt = 10 mV/µs,
12.5
SVSLFP = 1
t(SVSL)
SVSL on/off delay time
µs
SVSLE = 0
→ 1, dVCORE/dt = 1 mV/µs,
100
SVSLFP = 0
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
I(SVML)
SVML current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
µA
SVMLE = 1, dVCORE/dt = 10 mV/µs,
2.5
SVMLFP = 1
tpd(SVML)
SVML propagation delay
µs
SVMLE = 1, dVCORE/dt = 1 mV/µs,
20
SVMLFP = 0
SVMLE = 0
→ 1, dVCORE/dt = 10 mV/µs,
12.5
SVMLFP = 1
t(SVML)
SVML on/off delay time
µs
SVMLE = 0
→ 1, dVCORE/dt = 1 mV/µs,
100
SVMLFP = 0
Wake-up from Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Wake-up time from
PMMCOREV = SVSMLRRL = n, where n = 0,
fMCLK ≥ 4.0 MHz
5
tWAKE-UP-
LPM2, LPM3, or LPM4
1, 2, or 3
µs
FAST
fMCLK < 4.0 MHz
6
to active mode(1)
SVSLFP = 1
Wake-up time from
tWAKE-UP-
PMMCOREV = SVSMLRRL = n, where n = 0, 1, 2, or 3
LPM2, LPM3 or LPM4 to
150
165
µs
SLOW
SVSLFP = 0
active mode(2)
Wake-up time from RST
tWAKE-UP-
or BOR event to active
2
3
ms
RESET
mode(3)
(1)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family
User's Guide (SLAU259).
(2)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family User's Guide (SLAU259).
(3)
This value represents the time from the wakeup event to the reset vector execution.
56
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