Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

CC430F5135IRGZ Datasheet(PDF) 40 Page - Texas Instruments

Click here to check the latest version.
Part No. CC430F5135IRGZ
Description  MSP430 SoC with RF Core
Download  118 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

CC430F5135IRGZ Datasheet(HTML) 40 Page - Texas Instruments

Back Button CC430F5135IRGZ Datasheet HTML 36Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 37Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 38Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 39Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 40Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 41Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 42Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 43Page - Texas Instruments CC430F5135IRGZ Datasheet HTML 44Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 40 / 118 page
background image
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F613x
CC430F612x
CC430F513x
SLAS554D – MAY 2009 – REVISED JULY 2010
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
–0.3 V to 4.1 V
–0.3 V to (VCC + 0.3 V),
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS)(2)
4.1 V Max
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS(2)
–0.3 V to 2.0 V
Input RF level at pins RF_P and RF_N
10 dBm
Diode current at any device terminal
±2 mA
Storage temperature range(3), Tstg
–55°C to 105°C
Maximum junction temperature, TJ
95°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages referenced to VSS.
(3)
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics CC430F51xx
Low-K board
48 QFN (RGZ)
98°C/W
qJA
Junction to ambient thermal resistance, still air
High-K board
48 QFN (RGZ)
28°C/W
Thermal Packaging Characteristics CC430F61xx
Low-K board
64 QFN (RGC)
83°C/W
qJA
Junction to ambient thermal resistance, still air
High-K board
64 QFN (RGC)
26°C/W
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply voltage range applied at all DVCC and AVCC
PMMCOREVx = 0 (default
1.8
3.6
V
pins(1) during program execution and flash programming
after POR)
VCC
with PMM default settings. Radio is not operational with
PMMCOREVx = 1
2.0
3.6
V
PMMCOREVx = 0, 1.(2)
Supply voltage range applied at all DVCC and AVCC
PMMCOREVx = 2
2.2
3.6
V
VCC
pins(1) during program execution, flash programming and
PMMCOREVx = 3
2.4
3.6
V
radio operation with PMM default settings.(2)
Supply voltage range applied at all DVCC and AVCC
pins(1) during program execution, flash programming and
PMMCOREVx = 2,
VCC
radio operation with PMMCOREVx = 2, high-side SVS
SVSHRVLx=SVSHRRRLx=1
2.0
3.6
V
level lowered (SVSHRVLx=SVSHRRRLx=1) or high-side
or SVSHE=0
SVS disabled (SVSHE=0).(3) (2)
Supply voltage applied at the exposed die attach VSS and
VSS
0
V
AVSS pin
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
85
°C
CVCORE
Recommended capacitor at VCORE
470
nF
CDVCC/
Capacitor ratio of capacitor at DVCC to capacitor at
10
CVCORE
VCORE
PMMCOREVx = 0
0
8
MHz
(default condition)
PMMCOREVx = 1
0
12
MHz
fSYSTEM
Processor (MCLK) frequency(4) (see Figure 2)
PMMCOREVx = 2
0
16
MHz
PMMCOREVx = 3
0
20
MHz
(1)
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2)
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3)
Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation but the core voltage
will still stay within it's limits and is still supervised by the low-side SVS ensuring reliable operation.
(4)
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
40
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn