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PC912XDP512F0CAGR Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0CAGR Datasheet(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 1348 page  Chapter 1 Device Overview MC9S12XD-Family MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 73 Table 1-12. Interrupt Vector Locations (Sheet 1 of 3) Vector Address1 XGATE Channel ID2 Interrupt Source CCR Mask Local Enable $FFFE — System reset or illegal access reset None None $FFFC — Clock monitor reset None PLLCTL (CME, SCME) $FFFA — COP watchdog reset None COP rate select Vector base + $F8 — Unimplemented instruction trap None None Vector base+ $F6 — SWI None None Vector base+ $F4 — XIRQ X Bit None Vector base+ $F2 — IRQ I bit IRQCR (IRQEN) Vector base+ $F0 $78 Real time interrupt I bit CRGINT (RTIE) Vector base+ $EE $77 Enhanced capture timer channel 0 I bit TIE (C0I) Vector base + $EC $76 Enhanced capture timer channel 1 I bit TIE (C1I) Vector base+ $EA $75 Enhanced capture timer channel 2 I bit TIE (C2I) Vector base+ $E8 $74 Enhanced capture timer channel 3 I bit TIE (C3I) Vector base+ $E6 $73 Enhanced capture timer channel 4 I bit TIE (C4I) Vector base+ $E4 $72 Enhanced capture timer channel 5 I bit TIE (C5I) Vector base + $E2 $71 Enhanced capture timer channel 6 I bit TIE (C6I) Vector base+ $E0 $70 Enhanced capture timer channel 7 I bit TIE (C7I) Vector base+ $DE $6F Enhanced capture timer overflow I bit TSRC2 (TOF) Vector base+ $DC $6E Pulse accumulator A overflow I bit PACTL (PAOVI) Vector base + $DA $6D Pulse accumulator input edge I bit PACTL (PAI) Vector base + $D8 $6C SPI0 I bit SPI0CR1 (SPIE, SPTIE) Vector base+ $D6 $6B SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) Vector base + $D4 $6A SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) Vector base + $D2 $69 ATD0 I bit ATD0CTL2 (ASCIE) Vector base + $D2 Reserved Vector base + $D0 $68 ATD1 I bit ATD1CTL2 (ASCIE) Vector base + $CE $67 Port J I bit PIEJ (PIEJ7-PIEJ0) Vector base + $CC $66 Port H I bit PIEH (PIEH7-PIEH0) Vector base + $CA $65 Modulus down counter underflow I bit MCCTL(MCZI) Vector base + $C8 $64 Pulse accumulator B overflow I bit PBCTL(PBOVI) Vector base + $C6 $63 CRG PLL lock I bit CRGINT(LOCKIE) Vector base + $C4 $62 CRG self-clock mode I bit CRGINT (SCMIE) Vector base + $C2 Reserved Vector base + $C0 $60 IIC0 bus I bit IBCR0 (IBIE) |
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