 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
56F8013 Datasheet(PDF) 83 Page - Freescale Semiconductor, Inc |
|
||||||||||||||||||||||||||||||
56F8013 Datasheet(HTML) 83 Page - Freescale Semiconductor, Inc |
|
|
83 / 126 page  Clocks 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor 83 6.7 Clocks The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the exception of the Quad Timer and PWM peripheral clocks, which have the option (using TCR and PCR) to operate three times faster. The SIM is responsible for stalling individual clocks as a response to various hold-off requests, low power modes, and other configuration parameters. The SIM has access to the following signals from the OCCS module: While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks, the ADC standby and conversion clocks are generated by a direct interface between the ADC and the OCCS module. Figure 6-16 illustrates clock relationships to one another and to the various resets as the device comes out of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external reset, COP and Software reset). In the 56F8013/56F8011 architecture, this signal will be stretched by the SIM for a period of time (up to 96 MSTR_OSC clock cycles, depending upon the status of the POR) to create the clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. MSTR_OSC This comes from the input clock source mux of the OCCS. It is the output of the relaxation oscillator or the external clock source, depending on PRECS. It is not guaranteed to be at 50% duty cycle (+ or - 10% can probably be assumed for design purposes). This clock runs continuously, even during resetm and is used for reset generation. HS_PERF The PLL multiplies the MSTR_OSC by 24, to a maximum of 192MHz. The ZSRC field in OCCS selects the active source to be the PLL. This is divided by 2 and postscaled to produce this maximum 96MHz clock. It is used without further division to produce the high-speed (3x system bus rate) variants of the Quad Timer and PWM peripheral clocks. This clock is disabled when ZSRC is selecting MSTR_OSC. SYS_CLK_x2 The PLL can multiply the MSTR_OSC by 24, to a maximum of 192MHz. When the PLL is selected by the OCCS ZSRC field, the PLL is divided by three and postscaled to produce this maximum 64MHz clock. When MSTR_OSC is selected by the OCCS ZSRC field, MSTR_OSC feeds SYS_CLK_x2 directly. The SIM takes this clock and divides it by two to generate all the normal (1x system bus rate) peripheral and system clocks. |
Similar Part No. - 56F8013_08 |
|
Similar Description - 56F8013_08 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
