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PAC7202MPV70 Datasheet(PDF) 83 Page - Freescale Semiconductor, Inc |
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PAC7202MPV70 Datasheet(HTML) 83 Page - Freescale Semiconductor, Inc |
83 / 976 page Features MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 5 — General purpose I/O functionality on pins when not used for SPI • Two Asynchronous Enhanced Serial Communications Interface features (eSCI) — Standard Non return-to-Zero (NRZ) Mark/Space Format. — Full-Duplex Operation. — Software Selectable Word Length (8-bit or 9-bit words). — 10/11 or 13/14 bit Break Character possible. — 13-Bit Programmable Baud-Rate Modulus Counter. — Separately Enabled Transmitter and Receiver. — Separate receiver and transmitter CPU interrupt requests. — Programmable transmitter output polarity. — Two Receiver wake-up methods. — Interrupt-driven operation with eight flags. — Receiver framing error detection. — Hardware Parity Checking. — 1/16 bit time noise reduction. — LIN Master mode state machine – Supports generation of LIN message header. – Detection and flagging of LIN errors. — Two DMA request lines on each peripheral for receive and transmit data. • Inter IC Bus module features (IIC) — Compatibility with I2C Bus standard. — Two wire bi-directional serial bus for on board communications. — Multimaster operation. — Software-programmable for one of 256 different serial clock frequencies. — Software-selectable acknowledge bit. — Interrupt-driven byte-by-byte data transfer. — Arbitration-lost interrupt with automatic mode switching from master to slave. — Calling address identification interrupt. — Start and stop signal generation/detection. — Repeated START signal generation. — Acknowledge bit generation/detection — Bus-busy detection. — Two DMA request lines to receive and transmit data • Oscillator — Low power Amplitude Level Control (ALC) Oscillator. — Selectable oscillator mode at powerup or after a loss of clock • Clock generation |
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