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PAC7202VPV70 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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PAC7202VPV70 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 976 page MAC7200 Microcontroller Family Reference Manual, Rev. 2 vi Freescale Semiconductor 4.3.35 PD[1] / BWE[1] / MODA — Port D I/O Pin, External Bus Control & Mode Selection ....................................................................................................................46 4.3.36 PD[2] / CLKOUT / XCLKS — Clock Out and Oscillator Selection ............................46 4.3.37 PD[3] / XIRQ / NMI — Port D I/O Pin, High Priority Interrupt and Non-maskable Interrupt .....................................................................................................................47 4.3.38 PD[4] / IRQ — Port D I/O Pin, and Maskable Interrupt ...............................................47 4.3.39 PD[5:10] / ADDR[16:21] — Port D I/O Pins and External Address Bus.....................47 4.3.40 PD[11] / OE — Port D I/O Pin and External Bus Control ............................................47 4.3.41 PD[12] / Burst — Port D I/O Pin and External Bus Control.........................................47 4.3.42 PD[13] / TA — Port D I/O Pin and External Bus Control ............................................47 4.3.43 PD[15] / CS0 — Port D I/O Pin and External Bus Control...........................................48 4.3.44 PD[15] / R/W — Port D I/O Pin and External Bus Control ..........................................48 4.3.45 PE[0:15] / AN_A[00:15]— Port E I/O Pins and ATD_A..............................................48 4.3.46 PF[0] / EMIOS[0] / NEXPS — Port F I/O Pins, eMIOS Channels and Nexus Port Selection ....................................................................................................................48 4.3.47 PF[1] / EMIOS[1] / NEXPR — Port F I/O Pins, eMIOS Channels and Nexus Present Selection ....................................................................................................................48 4.3.48 PF[2] / EMIOS[2] / AUTOACK — Port F I/O Pins, eMIOS Channels and FlexBus Ack Selection.............................................................................................................49 4.3.49 PF[3] / EMIOS[3] / AUTOACK — Port F I/O Pins, eMIOS Channels and FlexBus Port Size.....................................................................................................................49 4.3.50 PF[4:7] / EMIOS[4:7] — Port F I/O Pins and eMIOS Channels ..................................49 4.3.51 PF[8] / PCS[5] / PCSS — Port F I/O Pin and DSPI_C .................................................49 4.3.52 PF[9] / PCS[3] — Port F I/O Pin and DSPI_C..............................................................50 4.3.53 PF[10] / PCS[2] — Port F I/O Pin and DSPI_C............................................................50 4.3.54 PF[11] / SCK_C — Port F I/O Pin and DSPI_C ...........................................................50 4.3.55 PF[12] / PCS[1] — Port F I/O Pin and DSPI_C............................................................50 4.3.56 PF[13] / SOUT_C — Port F I/O Pin and DSPI_C ........................................................50 4.3.57 PF[14] / PCS[0] / SS[0] — Port F I/O Pin and DSPI_C ...............................................50 4.3.58 PF[15] / SIN_C — Port F I/O Pin and DSPI_C ............................................................51 4.3.59 PG[0] / RXD_B — PORT G I/O Pin and ESCI_B........................................................51 4.3.60 PG[1] / TXD_B — PORT G I/O Pin and ESCI_B ........................................................51 4.3.61 PG[2] / RXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus Primary.......51 4.3.62 PG[3] / TXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus Primary.......51 4.3.63 PG[4] / TCNTX_A / NEX1MDO[2] — PORT G I/O Pin, FlexCAN_A and Nexus Primary ......................................................................................................................52 4.3.64 PG[5] / CNRX_A — PORT G I/O Pin and FlexCAN_A..............................................52 4.3.65 PG[6] / CNTX_B — PORT G I/O Pin and FlexCAN_B ..............................................52 4.3.66 PG[7] / CNRX_B — PORT G I/O Pin and FlexCAN_B ..............................................52 4.3.67 PG[8] — PORT G I/O Pin .............................................................................................52 4.3.68 PG[9] — PORT G I/O Pin .............................................................................................53 4.3.69 PG[10] — PORT G I/O Pin ...........................................................................................53 4.3.70 PG[11] — PORT G I/O Pin ...........................................................................................53 4.3.71 PG[12] / PCS[4] — Port G I/O Pin and DSPI_A ..........................................................53 4.3.72 PG[13] / PCS[3] — Port G I/O Pin and DSPI_A ..........................................................53 |
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