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PAC7202CPV70 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc |
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PAC7202CPV70 Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 976 page  MAC7200 Microcontroller Family Reference Manual, Rev. 2 xlvi Freescale Semiconductor 25-4 Debug Status Port (DEBUGPORT) Register ......................................................................454 25-5 Error Configuration (ERROR) Register ..............................................................................455 25-6 System Reset (SYSRESET) Register ..................................................................................457 26-1 Block diagram of PIT...........................................................................................................462 26-2 PIT RTI Load Value Register (TLVAL0) ...........................................................................467 26-3 PIT Timer Load Value Registers (TLVAL1–10) ................................................................468 26-4 PIT Current RTI Value (TVAL0) ........................................................................................469 26-5 PIT CurrentTimer Values (TVAL1–10) ..............................................................................470 26-6 APIT Interrupt Flags Register (PITFLG) ............................................................................471 26-7 PIT Interrupt Enable Register (PITINTEN) ........................................................................472 26-8 PIT Interrupt/DMA Select Registers (PITINTSEL) ............................................................473 26-9 PIT Timer Enable Register (PITEN) ...................................................................................474 26-10 PIT Control Registers (PITCTRL).......................................................................................475 26-11 Stopping and Starting a Timer .............................................................................................476 26-12 Modifying Running Timer Period .......................................................................................476 26-13 Dynamically Setting a New Load Value .............................................................................477 27-1 DMA Channel Mux .............................................................................................................481 27-2 Channel Configuration Registers (CHCONFIGxx).............................................................484 27-3 DMA Mux Channel 0-7 Block Diagram .............................................................................487 27-4 DMA Mux Channel Triggering: Normal Operation ............................................................487 27-5 DMA Mux Channel Triggering: Ignored Trigger................................................................488 27-6 DMA Mux Channel 8-15 Block Diagram ...........................................................................489 28-1 FlexCAN Block Diagram ....................................................................................................506 28-2 Message Buffer Structure ....................................................................................................512 28-3 Module Configuration Register (MCR)...............................................................................514 28-4 Control Register (CTRL) .....................................................................................................518 28-5 Free Running Timer (TIMER).............................................................................................521 28-6 Rx Global Mask Register (RXGMASK) .............................................................................521 28-7 Error Counter Register (ECR) .............................................................................................523 28-8 Error and Status Register (ESR) ..........................................................................................524 28-9 Interrupt Masks 1 Register (IMASK1) ................................................................................526 28-10 Interrupt Flags 1 Register (IFLAG1) ...................................................................................527 28-11 Rx Individual Mask Registers (RXIMR0–RXIMR63)........................................................528 28-12 CAN Engine Clocking Scheme ...........................................................................................535 28-13 Segments within the Bit Time..............................................................................................536 28-14 Arbitration, Match and Move Time Windows.....................................................................537 29-1 I2C Block Diagram ..............................................................................................................546 29-2 I2C Module DMA Interface Block Diagram .......................................................................547 29-3 Key to Register Fields..........................................................................................................550 29-4 I2C Bus Address Register (IBAD).......................................................................................550 29-5 I2C Bus Frequency Divider Register (IBFD).......................................................................550 29-6 SDA Hold Time ...................................................................................................................552 29-7 SCL Divider and SDA Hold ................................................................................................552 29-8 I2C Bus Control Register (IBCR) ........................................................................................557 29-9 I2C Bus Status Register(IBSR) ............................................................................................558 |
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