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PAC7202CPV70 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc |
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PAC7202CPV70 Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc |
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30 / 976 page  MAC7200 Microcontroller Family Reference Manual, Rev. 2 xxx Freescale Semiconductor 30.10.2.7 SOUT — Serial Output ...........................................................................................583 30.10.2.8 SCK — Serial Clock................................................................................................583 30.11 Memory Map and Register Definition.............................................................................583 30.11.1 Memory Map ...............................................................................................................583 30.11.2 Register Descriptions...................................................................................................584 30.11.2.1 DSPI Module Configuration Register (DSPI_MCR) ..............................................584 30.11.2.2 DSPI Transfer Count Register (DSPI_TCR) ...........................................................586 30.11.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTAR0–DSPI_CTAR7)...........................................................................587 30.11.2.4 DSPI Status Register (DSPI_SR) ............................................................................592 30.11.2.5 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) .............594 30.11.2.6 DSPI PUSH TX FIFO Register (DSPI_PUSHR) ....................................................596 30.11.2.7 DSPI POP RX FIFO Register (DSPI_POPR) .........................................................597 30.11.2.8 DSPI Transmit FIFO Registers 0–3 (DSPI_TXFR0–DSPI_TXFR3) .....................598 30.11.2.9 DSPI Receive FIFO Registers 0–3 (DSPI_RXFR0–DSPI_RXFR3) ......................599 30.12 Functional Description.....................................................................................................599 30.12.1 Modes of Operation .....................................................................................................600 30.12.1.1 Master Mode ............................................................................................................601 30.12.1.2 Slave Mode ..............................................................................................................601 30.12.1.3 Module Disable Mode .............................................................................................601 30.12.1.4 External Stop Mode .................................................................................................601 30.12.1.5 Debug Mode ............................................................................................................601 30.12.2 Start and Stop of DSPI Transfers .................................................................................602 30.12.3 Serial Peripheral Interface (SPI) Configuration...........................................................602 30.12.3.1 Master Mode ............................................................................................................603 30.12.3.2 Slave Mode ..............................................................................................................603 30.12.3.3 FIFO Disable Operation ..........................................................................................603 30.12.3.4 Transmit First In First Out (TX FIFO) Buffering Mechanism ................................604 30.12.3.4.1 Filling the TX FIFO.............................................................................................604 30.12.3.4.2 Draining the TX FIFO .........................................................................................604 30.12.3.5 Receive First In First Out (RX FIFO) Buffering Mechanism .................................604 30.12.3.5.1 Filling the RX FIFO ............................................................................................605 30.12.3.5.2 Draining the RX FIFO .........................................................................................605 30.12.4 DSPI Baud Rate and Clock Delay Generation ............................................................605 30.12.4.1 Baud Rate Generator................................................................................................606 30.12.4.2 PCS to SCK Delay (tCSC)........................................................................................606 30.12.4.3 After SCK Delay (tASC)...........................................................................................606 30.12.4.4 Delay after Transfer (tDT) .......................................................................................606 30.12.4.5 Peripheral Chip Select Strobe Enable (PCSS).........................................................607 30.12.5 Transfer Formats ..........................................................................................................608 30.12.5.1 Classic SPI Transfer Format (CPHA = 0) ...............................................................608 30.12.5.2 Classic SPI Transfer Format (CPHA = 1) ...............................................................609 30.12.5.3 Modified Transfer Format (MTFE = 1, CPHA = 0) ................................................610 30.12.5.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) .........................................611 30.12.5.5 Continuous Selection Format ..................................................................................612 |
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