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CAT5221YI10 Datasheet(PDF) 10 Page - ON Semiconductor |
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CAT5221YI10 Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 16 page CAT5221 Doc. No. MD-2113 Rev. M 10 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non- volatile memory and takes a maximum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5221; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. — Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 9). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5221 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail. Figure 7. Two-Byte Instruction Sequence Figure 8. Three-Byte Instruction Sequence Figure 9. Increment/Decrement Instruction Sequence S T A R T 01 0 1 A2 A0 A C K I2 I1 I0 R1 R0 A C K SDA S T O P ID3 ID2 ID1 ID0 Device ID Internal Instruction Opcode Address Register Address 0 P0 Pot/WCR Address A1 A3 I3 I3 I2 I1 I0 R1 R0 ID3 ID2 ID1ID0 Device ID Internal Instruction Opcode Address Data Register Address WCR[7:0] or Data Register D[7:0] S T A R T 01 0 1 A2 A1 A0 A C K Pot/WCR Address 0 P0 A C K SDA S T O P A C K D7 D6 D5 D4 D3 D2 D1 D0 A3 I3 I2 I1 I0 ID3 ID2 ID1 ID0 Device ID Internal Instruction Opcode Address Data Register Address S T A R T 01 01 A2 A1 A0 A C K R0 Pot/WCR Address 0P0 A C K SDA S T O P I N C 1 I N C 2 I N C n D E C 1 D E C n R1 A3 |
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