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CAT5221WI50 Datasheet(PDF) 8 Page - ON Semiconductor

Part # CAT5221WI50
Description  Dual Digitally Programmable Potentiometer (DPP?? with 64 Taps and I2C Interface
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT5221WI50 Datasheet(HTML) 8 Page - ON Semiconductor

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CAT5221
Doc. No. MD-2113 Rev. M
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
INSTRUCTIONS AND REGISTER
DESCRIPTION
INSTRUCTIONS
SLAVE ADDRESS BYTE
The first byte sent to the CAT5221 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5221 are
fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the CAT5221 to successfully continue the com–
mand sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3 - A0 inputs
can be actively driven by CMOS input signals or tied
to VCC or VSS.
INSTRUCTION BYTE
The next byte sent to the CAT5221 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The P0 bit points to one of the Wiper
Control Registers. The least two significant bits, R1
and R0, point to one of the four data registers of each
associated potentiometer. The format is shown in
Table 2.
Data Register Selection
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
ID3
ID2
ID1
ID0
A3
A2
A1
A0
010
1
(MSB)
(LSB)
Device Type
Identifier
Slave Address
I3
I2
I1
I0
R1
R0
0P0
(MSB)
(LSB)
Instruction
Data Register
WCR/Pot Selection
Opcode
Selection


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