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STE100P Datasheet(PDF) 1 Page - STMicroelectronics |
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STE100P Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 31 page 1/31 STE100P February 2006 1 DESCRIPTION The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer in- terface for 10Base-T and 100Base-TX applica- tions. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Control- lers (MAC) and a physical media interface for 100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3. The STEPHY1 supports both half-duplex and full- duplex operation, at 10 and 100 Mbps operation. Its operating mode can be set using auto-negotia- tion, parallel detection or manual control. It also al- lows for the support of auto-negotiation functions for speed and duplex detection. 2FEATURES 2.1 Industry standard ■ IEEE802.3u 100Base-TX and IEEE802.3 10Base-T compliant ■ Support for IEEE802.3x flow control ■ IEEE802.3u Auto-Negotiation support for 10Base-T and 100Base-TX ■ MII interface ■ Standard CSMA/CD or full duplex operation supported ■ Industrial temperature compliant 10/100 FAST ETHERNET 3.3V TRANSCEIVER Figure 2. Block Diagram NRZ To Manchester Encoder 10 TX Filter TRANSMITTER 10/100 Scrambler Auto Negotiation 4B/5B NRZ To NRZI Encoder Link Pulse Generator Binary To MLT3 Encoder RECEIVER 10/100 Parallel to Serial Descrambler Code Align 4B/5B NRZI To NRZ Decoder Serial to Parallel NRZ To Manchester Encoder Link Pulse Detector SMART Squelch 10 TX Filter Clock Recovery Clock Generation System Clock Adaptive Equalization BaseLine Wander Binary To MLT3 Decoder Clock Recovery REGISTERS HW Config Power Down LEDS RX Channel TX Channel TXP TXN RXP RXN MDC MDIO RXD[3:0] RX_ER RX_DV RX_CLK TX_CLK TXD[3:0] TX_ER TX_EN LEDS HW configuration pins 10Mb/s 100Mb/s 100Mb/s 10Mb/s Loopback Rev. 19 Figure 1. Package Table 1. Order Codes (*) ECOPACK® (see Section 9) Part Number Package STE100P TQFP64 E-STE100P (*) TQFP64 TQFP64 (10x10x1.40mm) |
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