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CAT823STDI-GT3 Datasheet(PDF) 7 Page - ON Semiconductor |
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CAT823STDI-GT3 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 15 page CAT823, CAT824, CAT825 © 2010 SCILLC. All rights reserved. 7 Doc. No. MD-3027, Rev. D Characteristics subject to change without notice FUNCTIONAL DESCRIPTION PROCESSOR RESET The CAT823-825 detect supply voltage (VCC) conditions that are below the specified voltage trip value (VRST) and provide a reset output to maintain correct system operation. On power-up, RESET ¯¯¯¯¯¯ (and RESET if available) are kept active for a minimum delay tRP of 140ms after the supply voltage (VCC) rises above VRST to allow the power supply and processor to stabilize. When VCC drops below the voltage trip value (VRST), the reset output signals RESET ¯¯¯¯¯¯ (and RESET) are pulled active. RESET ¯¯¯¯¯¯ (and RESET if available) is specifically designed to provide the reset input signals for processors. This provides reliable and consistent operation as power is turned on, off or during brownout conditions by maintaining the processor operation in known conditions. MANUAL RESET The CAT823 and CAT825 each have a Manual Reset (MR ¯¯¯) input to allow for alternative control of the reset outputs. The MR ¯¯¯ input is designed for direct con- nection to a pushbutton (see Figure 1). The MR ¯¯¯ input is internally pulled up by 52k Ω resistor and must be pulled low to cause the reset outputs to go active. Internally, this input is debounced and timed such that RESET ¯¯¯¯¯¯ (and RESET) signals of at least 140ms minimum will be generated. The min 140ms tRP delay commences as the Manual Reset input is released from the low level. (see Figure 2) Figure 1. Pushbutton RESET Figure 2. Timing Diagram – Pushbutton RESET VIL VIH VOH tRP tPDLY tPB VOL RESET RESET MR RESET CAT825 VCC RESET GND MR Supply Voltage |
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Similar Description - CAT823STDI-GT3 |
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