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CAT706TVI-G Datasheet(PDF) 7 Page - ON Semiconductor |
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CAT706TVI-G Datasheet(HTML) 7 Page - ON Semiconductor |
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7 / 14 page  CAT705, CAT706, CAT813 © 2010 SCILLC. All rights reserved. 7 Doc. No. MD-3030, Rev. D Characteristics subject to change without notice FUNCTIONAL DESCRIPTION PROCESSOR RESET The CAT705, CAT706 & CAT813 detect supply voltage (VCC) conditions that are below the specified voltage trip value (VRST) and provide a reset output to maintain correct system operation. On power-up, RESET ¯¯¯¯¯¯ (or RESET for the CAT813) are kept active for a minimum delay tRP of 140ms after the supply voltage (VCC) rises above VRST to allow the power supply and processor to stabilize. When VCC drops below the voltage trip value (VRST), the reset output signals RESET ¯¯¯¯¯¯ (or RESET) are pulled active. RESET ¯¯¯¯¯¯ (or RESET) is specifically designed to provide the reset input signals for processors. This provides reliable and consistent operation as power is turned on, off or during brownout conditions by maintaining the processor operation in known conditions. MANUAL RESET The CAT705, CAT706 & CAT813 each have a Manual Reset (MR ¯¯¯) input to allow for alternative control of the reset outputs. The MR ¯¯¯ input is designed for direct connection to a pushbutton (see Figure 1). The MR ¯¯¯ input is internally pulled up by 52k Ω resistor and must be pulled low to cause the reset output to go active. Internally, this input is debounced and timed such that RESET ¯¯¯¯¯¯ (or RESET) signals of at least 140ms minimum will be generated. The min 140ms tRP delay commences as the Manual Reset input is released from the low level. (see Figure 2) WDO PFO VCC WDI GND PFI MR RESET/RESET CAT705 CAT706 CAT813 Figure 1. Pushbutton RESET Figure 2. Timing Diagram – Pushbutton RESET VIL VIH VOH tRP tPDLY tPB VOL RESET RESET MR |
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