Electronic Components Datasheet Search |
|
CAT525LI Datasheet(PDF) 6 Page - ON Semiconductor |
|
CAT525LI Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 16 page CAT525 Not Recommended for New Design Doc. No. MD-2001 Rev. J 6 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice PIN DESCRIPTION Pin Name Function 1 VREFH2 Maximum DPP 2 output voltage 2 VREFH1 Maximum DPP 1 output voltage 3 VDD Power supply positive 4 CLK Clock input pin 5 RDY/BSY ¯¯¯¯ Ready/Busy output 6 CS Chip select 7 DI Serial data input pin 8 DO Serial data output pin 9 PROG Non-volatile Memory Programming Enable Input 10 GND Power supply ground 11 VREFL1 Minimum DPP 1 output voltage 12 VREFL2 Minimum DPP 2 output voltage 13 VREFL3 Minimum DPP 3 output voltage 14 VREFL4 Minimum DPP 4 output voltage 15 VOUT4 DPP 4 output 16 VOUT3 DPP 3 output 17 VOUT2 DPP 2 output 18 VOUT1 DPP 1 output 19 VREFH4 Maximum DPP 4 output voltage 20 VREFH3 Maximum DPP 3 output voltage CDPP/DPP addressing is as follows: DPP OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 DEVICE OPERATION The CAT525 is a quad 8-bit configured digitally programmable potentiometer (DPP/CDPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each confitured DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT525 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT525’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30ns to 90ns filter circuit to |
Similar Part No. - CAT525LI |
|
Similar Description - CAT525LI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |