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CAT64LC40LA-T3 Datasheet(PDF) 5 Page - ON Semiconductor |
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CAT64LC40LA-T3 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 12 page CAT64LC40 http://onsemi.com 5 Device Operation The CAT64LC40 is a 4 kb nonvolatile memory intended for use with all standard controllers. The CAT64LC40 is organized in a 256 x 16 format. All instructions are based on an 8−bit format. There are four 16−bit instructions: READ, WRITE, EWEN, and EWDS. The CAT64LC40 operates on a single power supply ranging from 2.5 V to 6.0 V and it has an on−chip voltage generator to provide the high voltage needed during a programming operation. Instructions, addresses and data to be written are clocked into the DI pin on the rising edge of the SK clock. The DO pin is normally in a high impedance state except when outputting data in a READ operation or outputting RDY/BSY status when polled during a WRITE operation. The format for all instructions sent to this device includes a 4−bit start sequence, 1010, a 4−bit op code and an 8−bit address field or dummy bits. For a WRITE operation, a 16−bit data field is also required following the 8−bit address field. SK DI DO RESET Figure 3. Synchronous Data Timing tRESS tRESH tRC tCSS CS RDY/BUSY tDIS tDIH tSKLOW tSKHI tCSH tCSMIN tHZ tSV tSV tPD0, tPD1 Figure 4. Read Instruction Timing *Please check the instruction set table for address SK DI DO RESET 1 ADDRESS* D15 D14 D1 D0 HIGH 01 0 1 0 0 0 CS RDY/BUSY |
Similar Part No. - CAT64LC40LA-T3 |
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Similar Description - CAT64LC40LA-T3 |
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