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MC68HCL05P1A Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc |
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MC68HCL05P1A Datasheet(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 124 page  MC68HC05P1A — Rev. 3.0 General Release Specification Memory General Release Specification — MC68HC05P1A Section 2. Memory 2.1 Introduction 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 Single-Chip Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 Input/Output (I/O) and Control Registers . . . . . . . . . . . . . . . . .25 2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .30 2.6 Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.2 Introduction The MC68HC05P1A utilizes 13 address lines to access an internal memory space covering 8 Kbytes. This memory space is divided into I/O, RAM, and ROM areas. 2.3 Single-Chip Mode Memory Map When the MC68HC05P1A is in the single-chip mode, the 32 bytes of I/O, 128 bytes of RAM, 2256 bytes of user ROM, 48 bytes of user page zero ROM, 32 bytes of test ROM, and 16 bytes of user vectors ROM are all active, as shown in Figure 2-1. 2.4 Input/Output (I/O) and Control Registers Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers at locations $0000–$001F. Reading unimplemented bits will return unknown states, and writing unimplemented bits will be ignored. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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