CAT64LC40

http://onsemi.com

6

The CAT64LC40 requires an active LOW CS in order to

be selected. Each instruction must be preceded by a

HIGH−to−LOW transition of CS before the input of the

4−bit start sequence. Prior to the 4−bit start sequence (1010),

the device will ignore inputs of all other logical sequence.

Read

Upon receiving a READ command and address (clocked

falling edge of the 16th clock (the last bit of the address

field). The READ operation is not affected by the RESET

input.

Write

After receiving a WRITE op code, address and data, the

device goes into the AUTO−Clear cycle and then the

WRITE cycle. The RDY/BSY pin will output the BUSY

(the last data bit) and will stay LOW until the write cycle is

complete. Then it will output a logical “1” until the next

WRITE cycle. The RDY/BSY output is not affected by the

input of CS.

SK

DI

DO

RESET

1

ADDRESS*

D15

D0

01

00

1

0

0

Figure 5. Write Instruction Timing

*Please check instruction set table for address.

CS

RDY/BUSY

SK

DI

CS

DO

RESET

WRITE INSTRUCTION

NEXT INSTRUCTION

HIGH

LOW

RDY/BUSY

Figure 6. Ready/BUSY Status Instruction Timing