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CAT64LC40VI-GT3 Datasheet(PDF) 7 Page - ON Semiconductor |
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CAT64LC40VI-GT3 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 12 page CAT64LC40 http://onsemi.com 7 An alternative to get RDY/BSY status is from the DO pin. During a write cycle, asserting a LOW input to the CS pin will cause the DO pin to output the RDY/BSY status. Bringing CS HIGH will bring the DO pin back to a high impedance state again. After the device has completed a WRITE cycle, the DO pin will output a logical “1” when the device is deselected. The rising edge of the first “1” input on the DI pin will reset DO back to the high impedance state again. The WRITE operation can be halted anywhere in the operation by the RESET input. If a RESET pulse occurs during a WRITE operation, the device will abort the operation and output a READY status. NOTE: Data may be corrupted if a RESET occurs while the device is BUSY. If the reset occurs before the BUSY period, no writing will be initiated. However, if RESET occurs after the BUSY period, new data will have been written over the old data. SK DI CS DO RESET 1 ADDRESS* D15 D0 RDY/BUSY 00 0 11 0 0 Figure 7. RESET During BUSY Instruction Timing tWR *Please check instruction set table for address. SK DI CS DO RESET 1 HIGH−Z HIGH RDY/BUSY 00 Figure 8. EWEN Instruction Timing 10 0 1 1 |
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Similar Description - CAT64LC40VI-GT3 |
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