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CAT64LC40LI-GT3 Datasheet(PDF) 4 Page - ON Semiconductor |
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CAT64LC40LI-GT3 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 12 page CAT64LC40 http://onsemi.com 4 Table 6. POWER−UP TIMING (Notes 8 and 9) Symbol Parameter Min Max Units tPUR Power−Up to Read Operation 10 ms tPUW Power−Up to Program Operation 1 ms 8. This parameter is tested initially and after a design or process change that affects the parameter. 9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Table 7. WRITE CYCLE LIMITS Symbol Parameter Min Max Units tWR Program Cycle Time 2.5 V 10 ms 4.5 V − 6.0 V 5 Table 8. INSTRUCTION SET Instruction Opcode Address Data Read 10101000 A7 A6 A5 A4 A3 A2 A1 A0 D15 − D0 Write 10100100 A7 A6 A5 A4 A3 A2 A1 A0 D15 − D0 Write Enable 10100011 X X X X X X X X Write Disable 10100000 X X X X X X X X [Write All Locations] (Note 10) 10100001 X X X X X X X X D15 − D0 10.(Write All Locations) is a test mode operation and is therefore not included in the AC/DC Operations specifications. INPUT PULSE LEVELS REFERENCE POINTS Figure 2. AC Testing Input/Output Waveform (Notes 11, 12 and 13) (CL = 100 pF) VCC x 0.3 VCC x 0.7 VCC x 0.8 VCC x 0.2 11. Input Rise and Fall Times (10% to 90%) < 10 ns. 12.Input Pulse Levels = VCC x 0.2 and VCC x 0.8. 13.Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7. |
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