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CAT28LV64JA-15T Datasheet(PDF) 5 Page - ON Semiconductor |
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CAT28LV64JA-15T Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 15 page CAT28LV64 http://onsemi.com 5 Figure 2. A.C. Testing Input/Output Waveform (Note 9) INPUT PULSE LEVELS REFERENCE POINTS 2.0 V 0.6 V 0.0 V VCC − 0.3 V 9. Input rise and fall times (10% and 90%) < 10 ns. Figure 3. A.C. Testing Load Circuit (example) DEVICE UNDER TEST 1.8 K OUTPUT 1. 3 K CL = 100 pF CL INCLUDES JIG CAPACITANCE VCC Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.) Symbol Parameter 28LV64−15 28LV64−20 28LV64−25 Units Min Max Min Max Min Max tWC Write Cycle Time 5 5 5 ms tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW (Note 10) CE Pulse Time 110 150 150 ns tOES OE Setup Time 0 10 10 ns tOEH OE Hold Time 0 10 10 ns tWP (Note 10) WE Pulse Width 110 150 150 ns tDS Data Setup Time 60 100 100 ns tDH Data Hold Time 0 0 0 ns tINIT (Note 11) Write Inhibit Period After Power−up 5 10 5 10 5 10 ms tBLC (Notes 11, 12) Byte Load Cycle Time 0.05 100 0.1 100 0.1 100 ms 10.A write pulse of less than 20 ns duration will not initiate a write cycle. 11. This parameter is tested initially and after a design or process change that affects the parameter. 12.A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. |
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