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CAT28C512H-12T Datasheet(PDF) 9 Page - ON Semiconductor |
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CAT28C512H-12T Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 12 page CAT28C512/513 9 Doc. No. MD-1007, Rev . I © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. HARDWARE DATA PROTECTION The following is a list of hardware data protection fea- tures that are incorporated into the CAT28C512/513. (1) VCC sense provides for write protection when VCC falls below 3.5V min. (2) A power on delay mechanism, tINIT (see AC charac- teristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 3.5V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28C512/513 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C512/513 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection Figure 10. Write Sequence for Deactivating Software Data Protection (1) SOFTWARE DATA PROTECTION ACTIVATED (12) WRITE DATA: XX WRITE LAST BYTE TO LAST ADDRESS TO ANY ADDRESS WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: A0 ADDRESS: 5555 WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: 80 ADDRESS: 5555 WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: 20 ADDRESS: 5555 |
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