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CAT24C128ZI-T3 Datasheet(PDF) 7 Page - ON Semiconductor |
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CAT24C128ZI-T3 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 14 page CAT24C128 http://onsemi.com 7 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SLAVE S T A R T ADDRESS BYTE ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+P A C K S T O P A C K A C K P A C K * = Don’t Care Bit P v 63 Figure 8. Page Write Sequence ** a13−a8 a7−a0 18 9 1 8 ADDRESS BYTE DATA BYTE SCL SDA WP Figure 9. WP Timing d0 d7 a7 a0 tHD:WP tSU:WP Read Operations Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the CAT24C128 will interpret this as a request for data residing at the current byte address in memory. The CAT24C128 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT24C128 returns to Standby mode. Selective Read To read data residing at a specific location, the internal address counter must first be initialized as described under Byte Write. If rather than following up the two address bytes with data, the Master instead follows up with an Immediate Read sequence, then the CAT24C128 will use the 14 active address bits to initialize the internal address counter and will shift out data residing at the corresponding location. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 11), the CAT24C128 returns to Standby mode. Sequential Read If during a Read session the Master acknowledges the 1st data byte, then the CAT24C128 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). |
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