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DSP56F801FA60 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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DSP56F801FA60 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 48 page  Interrupt and Program Control Signals 56F801 Technical Data, Rev. 17 Freescale Semiconductor 11 2.4 Interrupt and Program Control Signals 2.5 Pulse Width Modulator (PWM) Signals 1 XTAL GPIOB3 Output Input/ Output Chip- driven Input Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more information, please refer to Section 3.5.3. Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that can be programmed as an input or output pin. This I/O can be utilized when using the on-chip relaxation oscillator so the XTAL pin is not needed. Table 2-6 Interrupt and Program Control Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 1 IRQA Input (Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. 1 RESET Input (Schmitt) Input Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Table 2-7 Pulse Width Modulator (PWMA) Signals No. of Pins Signal Name Signal Type State During Reset Signal Description 6 PWMA0-5 Output Tri-stated PWMA0-5— These are six PWMA output pins. 1 FAULTA0 Input (Schmitt) Input FAULTA0— This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. Table 2-5 PLL and Clock (Continued) No. of Pins Signal Name Signal Type State During Reset Signal Description |
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