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ADT7473ARQZ-001 Datasheet(PDF) 4 Page - ON Semiconductor |
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ADT7473ARQZ-001 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 74 page ADT7473 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1) Parameter Unit Max Typ Min Conditions Digital Input Logic Levels (THERM) ADTL+ Input High Voltage, VIH 0.75 x VCC V Input Low Voltage, VIL 0.8 V Input High Voltage, VIH Input Low Voltage, VIL VIN = VCC ±1 mA Input Low Current, IIL VIN = 0 ±1 mA Input Capacitance, CIN 5.0 pF Serial Bus Timing (Note 2) (See Figure 2) Clock Frequency, fSCLK 10 400 kHz Glitch Immunity, tSW 50 ns Bus Free Time, tBUF 4.7 ms SCL Low Time, tLOW 4.7 ms SCL High Time, tHIGH 4.0 50 ms SCL, SDA Rise Time, tr 1,000 ns SCL, SDA Fall Time, tf 300 ms Data Setup Time, tSU; DAT 250 ns Detect Clock Low Timeout, tTIMEOUT Can be optionally disabled 15 35 ms 1. All voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA = 25°C and represent most likely parametric norm. Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. 2. Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested. Figure 2. Serial Bus Timing Diagram SCL SDA PS SP tBUF tHD: STA tHD: DAT tSU: DAT tF tR tLOW tSU: STA tHIGH tHD: STA tSU: STO |
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