ADT7468ARQ datasheet(4/81 Pages) ONSEMI

Part #	ADT7468ARQ

Description	dBCool짰 Remote Thermal Controller and Voltage Monitor

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Manufacturer	ONSEMI [ON Semiconductor]

Direct Link	http://www.onsemi.com

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ADT7468

Rev. 3 | Page 4 of 81 | www.onsemi.com

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OPEN-DRAIN DIGITAL OUTPUTS,

PWM1 TO PWM3, XTO

Current Sink, IOL

8.0

mA

Output Low Voltage, VOL

0.4

V

IOUT = −8.0 mA, VCC = +3.3 V

High Level Output Current, IOH

0.1

1.0

µA

VOUT = VCC

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

Output Low Voltage, VOL

0.4

V

IOUT = −4.0 mA, VCC = +3.3 V

High Level Output Current, IOH

0.1

1.0

µA

VOUT = VCC

SMBUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, VIH

2.0

V

Input Low Voltage, VIL

0.4

V

Hysteresis

500

mV

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Input High Voltage, VIH

2.0

V

5.5

V

Maximum input voltage

Input Low Voltage, VIL

0.8

V

−0.3

V

Minimum input voltage

Hysteresis

0.5

V p-p

DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+

Input High Voltage, VIH

0.75 × VCCP

V

Input Low Voltage, VIL

0.4

V

DIGITAL INPUT CURRENT

Input High Current, IIH

−1

µA

VIN = VCC

Input Low Current, IIL

1

µA

VIN = 0

Input Capacitance, CIN

5

pF

SERIAL BUS TIMING

See Figure 2

Clock Frequency, fSCLK

10

400

kHz

Glitch Immunity, tSW

50

ns

Bus Free Time, tBUF

4.7

µs

Start Setup Time, tSU;STA

4.7

µs

Start Hold Time, tHD;STA

4.0

µs

SCL Low Time, tLOW

4.7

µs

SCL High Time, tHIGH

4.0

50

µs

SCL, SDA Rise Time, tR

1000

ns

SCL, SDA Fall Time, tF

300

µs

Data Setup Time, tSU;DAT

250

ns

Data Hold Time, tHD;DAT

300

ns

Detect Clock Low Timeout, tTIMEOUT

15

35

ms

Can be optionally disabled

SCL

SDA

P

S

P

tBUF

tHD; STA

tHD; DAT

tSU; DAT

tF

tR

tLOW

tSU; STA

tHIGH

tHD; STA

tSU; STO

Figure 2. Serial Bus Timing Diagram

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