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ADP3208D Datasheet(PDF) 4 Page - ON Semiconductor

Part No. ADP3208D
Description  7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3208D Datasheet(HTML) 4 Page - ON Semiconductor

 
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ADP3208D
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PIN FUNCTION DESCRIPTIONS
Pin No
Mnemonic
Description
1
EN
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT
low, and pulls CLKEN high.
2
PWRGD
Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
3
NC
Not Connected.
4
CLKEN
Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to the
external clock.
5
FBRTN
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground
return for the VID DAC and the voltage error amplifier blocks.
6
FB
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
7
COMP
Voltage Error Amplifier Output and Frequency Compensation Point.
8
NC
Not Connected.
9
IRPM/NC
RPM Mode Timing Control Input. A resistor between this pin or RPM pin to ground sets the RPM mode
turn−on threshold voltage. If a resistor is connected between this pin to ground, RPM pin must remain
floating and not connected.
10
VARFREQ
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
11
VRTT
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
12
TTSNS
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is
connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is
connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the
thermal throttling function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.
13
IMON
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
14
RPM
RPM Mode Timing Control Input. A resistor between this pin or IRPM pin to ground sets the RPM mode
turn−on threshold voltage. If a resistor is connected between this pin to ground, IRPM pin must remain
floating.
15
IREF
This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground.
16
LLINE
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
17
CSCOMP
Current Sense Amplifier Output and Frequency Compensation Point.
18
CSREF
Current Sense Reference Input. This pin must be connected to the common point of the output inductors.
The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop
transient control of the converter output voltage.
19
CSSUM
Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currents
to provide total current information.
20
RAMP
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets
the slope of the internal PWM stabilizing ramp used for phase−current balancing.
21
ILIMN
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.
22
ILIMP
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.
23
RT
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator
frequency.
24
GND
Analog and Digital Signal Ground.
25
BST2
High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage
while the high−side MOSFET is on.
26
DRVH2
High−Side Gate Drive Output for Phase 2.
27
SW2
Current Balance Input for Phase 2 and Current Return for High−Side Gate Drive.
28
PVCC2
Power Supply Input/Output of Low−Side Gate Driver for Phase 2.
29
DRVL2
Low−Side Gate Drive Output for Phase 2.
30
PGND2
Low−Side Driver Power Ground for Phase 2.


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