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ADP3208D Datasheet(PDF) 35 Page - ON Semiconductor
ONSEMI [ON Semiconductor]
ADP3208D Datasheet(HTML) 35 Page - ON Semiconductor
/ 37 page
Layout and Component Placement
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
1. 1. For best results, use a PCB of four or more
layers. This should provide the needed versatility
for control circuitry interconnections with optimal
placement; power planes for ground, input, and
output; and wide interconnection traces in the rest
of the power delivery current paths. Keep in mind
that each square unit of 1 oz copper trace has a
resistance of ~0.53 m
W at room temperature.
2. When high currents must be routed between PCB
layers, vias should be used liberally to create
several parallel current paths so that the resistance
and inductance introduced by these current paths is
minimized and the via current rating is not
3. If critical signal lines (including the output voltage
sense lines of the ADP3208D) must cross through
power circuitry, it is best if a signal ground plane
can be interposed between those signal lines and
the traces of the power circuitry. This serves as a
shield to minimize noise injection into the signals
at the expense of increasing signal ground noise.
4. An analog ground plane should be used around
and under the ADP3208D for referencing the
components associated with the controller. This
plane should be tied to the nearest ground of the
output decoupling capacitor, but should not be tied
to any other power circuitry to prevent power
currents from flowing into the plane.
5. The components around the ADP3208D should be
located close to the controller with short traces.
The most important traces to keep short and away
from other traces are those to the FB and CSSUM
pins. Refer to Figure 42 for more details on the
layout for the CSSUM node.
6. The output capacitors should be connected as close
as possible to the load (or connector) that receives
the power (for example, a microprocessor core). If
the load is distributed, the capacitors should also
be distributed and generally placed in greater
proportion where the load is more dynamic.
7. Avoid crossing signal lines over the switching
power path loop, as described in the Power
1. The switching power path on the PCB should be
routed to encompass the shortest possible length to
minimize radiated switching noise energy (that is,
EMI) and conduction losses in the board. Failure
to take proper precautions often results in EMI
problems for the entire PC system as well as
noise−related operational problems in the
power−converter control circuitry. The switching
power path is the loop formed by the current path
through the input capacitors and the power
MOSFETs, including all interconnecting PCB
traces and planes. The use of short, wide
interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance
in the switching loop, which can cause high energy
ringing, and it accommodates the high current
demand with minimal voltage loss.
2. When a power−dissipating component (for
example, a power MOSFET) is soldered to a PCB,
the liberal use of vias, both directly on the
mounting pad and immediately surrounding it, is
recommended. Two important reasons for this are
improved current rating through the vias and
improved thermal performance from vias extended
to the opposite side of the PCB, where a plane can
more readily transfer heat to the surrounding air.
To achieve optimal thermal dissipation, mirror the
pad configurations used to heat sink the MOSFETs
on the opposite side of the PCB. In addition,
improvements in thermal performance can be
obtained using the largest possible pad area.
3. The output power path should also be routed to
encompass a short distance. The output power path
is formed by the current path through the inductor,
the output capacitors, and the load.
4. For best EMI containment, a solid power ground
plane should be used as one of the inner layers and
extended under all power components.
1. The output voltage is sensed and regulated
between the FB and FBRTN pins, and the traces of
these pins should be connected to the signal
ground of the load. To avoid differential mode
noise pickup in the sensed signal, the loop area
should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to
each other, atop the power ground plane, and back
to the controller.
2. The feedback traces from the switch nodes should
be connected as close as possible to the inductor.
The CSREF signal should be Kelvin connected to
the center point of the copper bar, which is the
common node for the inductors of all the
3. On the back of the ADP3208D package, there is a
metal pad that can be used to heat sink the device.
Therefore, running vias under the ADP3208D is
not recommended because the metal pad may
cause shorting between vias.
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