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ADP3208D Datasheet(PDF) 32 Page - ON Semiconductor

Part No. ADP3208D
Description  7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3208D Datasheet(HTML) 32 Page - ON Semiconductor

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ADP3208D
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32
A Type III compensator on the voltage feedback is
adequate for proper compensation of the output filter.
Figure 43 shows the Type III amplifier used in the
ADP3208D. Figure 44 shows the locations of the two poles
and two zeros created by this amplifier.
Figure 43. Voltage Error Amplifier
RA
CB
RFB
CA
CFB
COMP
FB
REFERENCE
VOLTAGE
VOLTAGE ERROR
AMPLIFIER
ADP3208D
OUTPUT
VOLTAGE
Figure 44. Poles and Zeros of Voltage Error Amplifier
GAIN
0dB
FREQUENCY
fP1
fZ2
fP2
fZ1
–20dB/DEC
–20dB/DEC
The following equations give the locations of the poles
and zeros shown in Figure 44:
fZ1 +
1
2p
CA RA
(eq. 29)
(eq. 30)
(eq. 31)
(eq. 32)
fZ2 +
1
2p
CFB RFB
fP1 +
1
2p CA ) CB
RFB
fP2 +
CA ) CB
2p
RA CB ) CA
The expressions that follow compute the time constants
for the poles and zeros in the system and are intended to yield
an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component
parasitic effects (see the Tuning Procedure for ADP3208D
section):
RE + n RO ) AD RDS )
RL VRT
VID
(eq. 33)
)
2
L
(1 * (n
D))
VRT
n
CX RO VVID
TA + CX (RO * R ) )
LX
RO
RO * R
RX
(eq. 34)
TB + (RX ) R * RO) CX
(eq. 35)
TC +
VRT
L *
AD RDS
2 fSW
VVID RE
(eq. 36)
TD +
CX CZ RO 2
CX (RO * R ) ) CZ RO
(eq. 37)
where:
R’ is the PCB resistance from the bulk capacitors to the
ceramics and is approximately 0.4 m
W (assuming an 8−layer
motherboard).
RDS is the total low−side MOSFET for on resistance per
phase.
AD is 5.
VRT is 1.25 V.
LX is 150 pH for the six Panasonic SP capacitors.
The compensation values can be calculated as follows:
CA +
n
RO TA
RE RB
(eq. 38)
RA +
TC
CA
(eq. 39)
CB +
TB
RB
(eq. 40)
CFB +
TD
RA
(eq. 41)
The standard values for these components are subject to
the tuning procedure described in the Tuning Procedure for
ADP3208D section.
CIN Selection and Input Current DI/DT Reduction
In continuous inductor−current mode, the source current
of the high−side MOSFET is approximately a square wave
with a duty ratio equal to n
× VOUT/VIN and amplitude that
is one−nth of the maximum output current. To prevent large
voltage transients, use a low ESR input capacitor sized for
the maximum RMS current. The maximum RMS capacitor
current occurs at the lowest input voltage and is given by:
ICRMS + D IO
1
n
D
* 1
(eq. 42)
ICRMS + 0.18 40 A
1
2
0.18
* 1 + 9.6 A
where IO is the output current.
In a typical notebook system, the battery rail decoupling
is achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
capacitor bank is formed by eight pieces of 10
mF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.


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