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ADP3208D Datasheet(PDF) 31 Page - ON Semiconductor

Part No. ADP3208D
Description  7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3208D Datasheet(HTML) 31 Page - ON Semiconductor

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ADP3208D
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31
The previous equation also shows the standby dissipation
(ICC times the VCC) of the driver.
Ramp Resistor Selection
The ramp resistor (RR) is used to set the size of the internal
PWM ramp. The value of this resistor is chosen to provide
the best combination of thermal balance, stability, and
transient response. Use the following expression to
determine a starting value:
RR +
AR L
3
AD RDS CR
RR +
0.5
360 nH
3
5
5.2 mW
5pF
+ 462 kW
(eq. 24)
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low−side MOSFET ON−resistance;
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of
the internal ramp voltage (see Equation 25). For stability and
noise immunity, keep the ramp size larger than 0.5 V. Taking
this into consideration, the value of RR in this example is
selected as 280 k
W.
The internal ramp voltage magnitude can be calculated as
follows:
VR +
AR (1 * D) VVID
RR CR fSW
VR +
0.5
(1 * 0.061)
1.150 V
462 kW
5pF
280 kHz
+ 0.83 V
(eq. 25)
The size of the internal ramp can be increased or
decreased. If it is increased, stability and transient response
improves but thermal balance degrades. Conversely, if the
ramp size is decreased, thermal balance improves but
stability and transient response degrade. In the denominator
of Equation 24, the factor of 3 sets the minimum ramp size
that produces an optimal combination of good stability,
transient response, and thermal balance.
COMP Pin Ramp
In addition to the internal ramp, there is a ramp signal on
the COMP pin due to the droop voltage and output voltage
ramps. This ramp amplitude adds to the internal ramp to
produce the following overall ramp signal at the PWM
input:
VRT +
VR
1 *
2 (1*n D)
n fSW CX RO
(eq. 26)
where CX is the total bulk capacitance, and RO is the droop
resistance of the regulator.
For this example, the overall ramp signal is 1.85 V.
Current Limit Setpoint
To select the current limit setpoint, the resistor value for
RCLIM must be determined. The current limit threshold for
the ADP3208D is set with RCLIM. RCLIM can be found using
the following equation:
RLIM +
ILIM RO
60 mA
(eq. 27)
where:
RLIM is the current limit resistor.
RO is the output load line.
ILIM is the current limit set point.
When the ADP3208D is configured for 2−phase
operation, the equation above is used to set the current limit.
When the ADP3208D switches from 2−phase to 1−phase
operation by PSI or DPRSLP signal, the current is
single−phase is one half of the current limit in 2−phase.
When the ADP3208D is configured for 1−phase
operation, the equation above is used to set the current limit.
Output Current Monitor
The ADP3208D has output current monitor. The IMON
pin sources a current proportional to the total inductor
current. A resistor, RMON, from IMON to FBRTN sets the
gain of the output current monitor. A 0.1
mF is placed in
parallel with RMON to filter the inductor current ripple and
high frequency load transients. Since the IMON pin is
connected directly to the CPU, it is clamped to prevent it
from going above 1.15V.
The IMON pin current is equal to the RLIM times a fixed
gain of 10. RMON can be found using the following equation:
RMON +
1.15 V
RLIM
10
RO IFS
(eq. 28)
where:
RMON is the current monitor resistor. RMON is connected
from IMON pin to FBRTN.
RLIM is the current limit resistor.
RO is the output load line resistance.
IFS is the output current when the voltage on IMON is at full
scale.
Feedback Loop Compensation Design
Optimized compensation of the ADP3208D allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (RO). With the resistive output impedance, the
output voltage droops in proportion with the load current at
any load current slew rate, ensuring the optimal position and
allowing the minimization of the output decoupling.
With the multi−mode feedback structure of the
ADP3208D, it is necessary to set the feedback compensation
so that the converter’s output impedance works in parallel
with the output decoupling. In addition, it is necessary to
compensate for the several poles and zeros created by the
output inductor and decoupling capacitors (output filter).


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