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ADP3208D Datasheet(PDF) 30 Page  ON Semiconductor 

ADP3208D Datasheet(HTML) 30 Page  ON Semiconductor 
30 / 37 page ADP3208D http://onsemi.com 30 LX is about 150 pH for the six SP capacitors, which is low enough to avoid ringing during a load change. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. For this multi−mode control technique, an all ceramic capacitor design can be used if the conditions of Equations 16, 17, and 18 are satisfied. Power MOSFETs For typical 20 A per phase applications, the N−channel power MOSFETs are selected for two high−side switches and two or three low−side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the voltage of the gate driver is 5.0 V, logic−level threshold MOSFETs must be used. The maximum output current, IO, determines the RDS(ON) requirement for the low−side (synchronous) MOSFETs. In the ADP3208D, currents are balanced between phases; the current in each low−side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO): PSF + (1 * D) IO nSF 2 ) 1 12 n IR nSF 2 RDS(SF) (eq. 19) where: D is the duty cycle and is approximately the output voltage divided by the input voltage. IR is the inductor peak−to−peak ripple current and is approximately: IR + (1 * D) VOUT L fSW (eq. 20) Knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required RDS(ON) for the MOSFET. For 8−lead SOIC or 8−lead SOIC−compatible MOSFETs, the junction−to−ambient (PCB) thermal impedance is 50 °C/W. In the worst case, the PCB temperature is 70 °C to 80°C during heavy load operation of the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W at 120 °C junction temperature. Therefore, for this example (40 A maximum), the RDS(SF) per MOSFET is less than 8.5 m W for two pieces of low−side MOSFETs. This RDS(SF) is also at a junction temperature of about 120°C; therefore, the RDS(SF) per MOSFET should be less than 6 mW at room temperature, or 8.5 m W at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. The high−side (main) MOSFET must be able to handle two main power dissipation components: conduction losses and switching losses. Switching loss is related to the time for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET: RRPM + 2 RT VVID 1.0 V AR (1 * D) VVID RR CR fSW * 0.5 kW (eq. 21) where: nMF is the total number of main MOSFETs. RG is the total gate resistance. CISS is the input capacitance of the main MOSFET. The most effective way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation: RRPM + 2 280 kW 1.150 V ) 1.0 V 0.5 (1 * 0.061) 1.150 462 kW 5pF 300 kHz (eq. 22) * 500 kW + 202 kW where RDS(MF) is the on resistance of the MOSFET. Typically, a user wants the highest speed (low CISS) device for a main MOSFET, but such a device usually has higher on resistance. Therefore, the user must select a device that meets the total power dissipation (about 0.8 W to 1.0 W for an 8−lead SOIC) when combining the switching and conduction losses. For example, an IRF7821 device can be selected as the main MOSFET (four in total; that is, nMF = 4), with approximately CISS = 1010 pF (max) and RDS(MF) = 18 mW (max at TJ = 120°C), and an IR7832 device can be selected as the synchronous MOSFET (four in total; that is, nSF = 4), with RDS(SF) = 6.7 mW (max at TJ = 120°C). Solving for the power dissipation per MOSFET at IO = 40 A and IR = 9.0 A yields 630 mW for each synchronous MOSFET and 590 mW for each main MOSFET. A third synchronous MOSFET is an option to further increase the conversion efficiency and reduce thermal stress. Finally, consider the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation: PDRV + (eq. 23) fSW 2 n nMF QGMF ) nSF QQSF ) ICC VCC where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET. 
