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ADP3208D Datasheet(PDF) 27 Page  ON Semiconductor 

ADP3208D Datasheet(HTML) 27 Page  ON Semiconductor 
27 / 37 page ADP3208D http://onsemi.com 27 Application Information The design parameters for a typical IMVP−6+ compliant CPU core VR application are as follows: • Maximum input voltage (VINMAX) = 19 V • Minimum input voltage (VINMIN) = 8.0 V • Output voltage by VID setting (VVID) = 1.4375 V • Maximum output current (IO) = 40 A • Droop resistance (RO) = 2.1 mW • Nominal output voltage at 40 A load (VOFL) = 1.3535 V • Static output voltage drop from no load to full load ( DV) = VONL − VOFL = 1.4375 V − 1.3535 V = 84 mV • Maximum output current step (DIO) = 27.9 A • Number of phases (n) = 2 • Switching frequency per phase (fSW) = 300 kHz • Duty cycle at maximum input voltage (DMAX) = 0.18 V • Duty cycle at minimum input voltage (DMIN) = 0.076 V Setting the Clock Frequency for PWM In PWM operation, the ADP3208D uses a fixed−frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. For a dual−phase design, a clock frequency of 600 kHz sets the switching frequency to 300 kHz per phase. This selection represents the trade−off between the switching losses and the minimum sizes of the output filter components. To achieve a 600 kHz oscillator frequency at a VID voltage of 1.2 V, RT must be 187 k W. Alternatively, the value for RT can be calculated by using the following equation: RT + VVID ) 1.0 V 2 n fSW 9pF * 16 kW (eq. 1) where: 9 pF and 16 k W are internal IC component values. VVID is the VID voltage in volts. n is the number of phases. fSW is the switching frequency in hertz for each phase. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. When VARFREQ pin is connected to ground, the switching frequency does not change with VID. The value for RT can be calculated by using the following equation. RT + 1.0 V n fSW 9pF * 16 kW (eq. 2) For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. Setting the Switching Frequency for RPM Operation of Phase 1 During the RPM mode operation of Phase 1, the ADP3208D runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. When considering power conversion efficiency in light load, lower switching frequency is usually preferred for RPM mode. However, the VCORE ripple specification in the IMVP−6 sets the limitation for lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM mode can be equal, larger, or smaller than its counterpart in PWM mode. A resistor from RPM to GND sets the pseudo constant frequency as following: PS(MF) + 2 fSW VCC IO nMF RG nMF n CISS (eq. 3) where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kW, the following resistance sets up 300 kHz switching frequency in RPM operation. PS(MF) + 2 fSW VCC IO nMF RG nMF n CISS (eq. 4) Inductor Selection The choice of inductance determines the ripple current of the inductor. Less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs. However, this allows the use of smaller−size inductors, and for a specified peak−to−peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger−size inductors and more output capacitance for the same peak−to−peak transient deviation. For a multiphase converter, the practical value for peak−to−peak inductor ripple current is less than 50% of the maximum dc current of that inductor. Equation 5 shows the relationship between the inductance, oscillator frequency, and peak−to−peak ripple current. Equation 6 can be used to determine the minimum inductance based on a given output ripple voltage. IR + VVID 1 * DMIN fSW L (eq. 5) L w VVID RO (1 * (n DMIN)) fSW VRIPPLE (eq. 6) Solving Equation 6 for a 16 mV peak−to−peak output ripple voltage yields L w 1.4375 V 2.1 mW (1 * (2 0.076) 300 kHz 16 mV + 533 nH (eq. 7) If the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 490 nH inductor is a good choice for a starting point, and it provides 
