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ADP3208D Datasheet(PDF) 20 Page - ON Semiconductor
ONSEMI [ON Semiconductor]
ADP3208D Datasheet(HTML) 20 Page - ON Semiconductor
/ 37 page
operation, the voltage on the I
pin is equal to the CSREF
pin. The voltage across R
is equal to the voltage across
the CSA (from CSREF pin to CSCOMP pin). This voltage
is proportional to output current. The current through R
is proportional to the output inductor current. The current
is compared with an internal reference
current. When the R
current goes above the internal
reference current, the ADP3208D goes into current limit.
The current limit circuit is shown in Figure 30.
Figure 30. Current Limit Circuit
During startup when the output voltage is below 200 mV,
a secondary current limit is activated. This is necessary
because the voltage swing on CSCOMP cannot extend
below ground. The secondary current limit circuit clamps
the internal COMP voltage and sets the internal
compensation ramp termination voltage at 1.5 V level. The
clamp actually limits voltage drop across the low side
MOSFETs through the current balance circuitry.
An inherent per phase current limit protects individual
phases in case one or more phases stop functioning because
of a faulty component. This limit is based on the maximum
normal mode COMP voltage.
After 9 ms in current limit, the ADP3208D will latchoff.
The latchoff can be reset by removing and reapplying VCC,
or by recycling the EN pin low and high for a short time.
The latchoff can be reset by removing and reapplying
VCC, or by recycling the EN pin low and high for a short
Figure 31. Current Overload
PWRGD 2.0 V/DIV
OUTPUT 0.5 V/DIV
Changing VID OTF
The ADP3208D is designed to track dynamically
changing VID code. As a consequence, the CPU VCC
voltage can change without the need to reset the controller
or the CPU. This concept is commonly referred to as VID
OTF transient. A VID OTF can occur with either light or
heavy load conditions. The processor alerts the controller
that a VID change is occurring by changing the VID inputs
in LSB incremental steps from the start code to the finish
code. The change can be either upwards or downwards steps.
When a VID input changes, the ADP3208D detects the
change but ignores new code for a minimum of 400 ns. This
delay is required to prevent the device from reacting to
digital signal skew while the 7−bit VID input code is in
transition. Additionally, the VID change triggers a PWRGD
masking timer to prevent a PWRGD failure. Each VID
change resets and retriggers the internal PWRGD masking
As listed in Table 3, during a VID transient, the
ADP3208D forces PWM mode regardless of the state of the
system input signals. For example, this means that if the chip
is configured as a dual−phase controller but is running in
single−phase mode due to a light load condition, a current
overload event causes the chip to switch to dual−phase mode
to share the excessive load until the delayed current limit
latchoff cycle terminates.
In user−set single−phase mode, the ADP3208D usually
runs in RPM mode. When a VID transition occurs, however,
the ADP3208D switches to dual−phase PWM mode.
Light Load RPM DCM Operation
In single−phase normal mode, DPRSLP is pulled low and
the APD3208 operates in Continuous Conduction Mode
(CCM) over the entire load range. The upper and lower
MOSFETs run synchronously and in complementary phase.
See Figure 32 for the typical waveforms of the ADP3208D
running in CCM with a 7 A load current.
Figure 32. Single−Phase Waveforms in CCM
OUTPUT VOLTAGE 20 mV/DIV
INDUCTOR CURRENT 5 A/DIV
SWITCH NODE 5.0 V/DIV
LOW−SIDE GATE 5.0 V/DIV
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