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ADP3208D Datasheet(PDF) 15 Page - ON Semiconductor

Part No. ADP3208D
Description  7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3208D Datasheet(HTML) 15 Page - ON Semiconductor

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ADP3208D
http://onsemi.com
15
Theory of Operation
The ADP3208D combines multi−mode Pulse Width
Modulated (PWM) control and Ramp Pulse Modulated
(RPM) control with multi−phase logic outputs for use in
single− and dual−phase synchronous buck CPU core supply
power converters. The internal 7−bit VID DAC conforms to
the Intel IMVP−6+ specifications.
Multiphase operation is important for producing the high
currents and low voltages demanded by today’s
microprocessors. Handling high currents in a single−phase
converter would put too high of a thermal stress on system
components such as the inductors and MOSFETs.
The multi−mode control of the ADP3208D is a stable,
high performance architecture that includes
Current and thermal balance between phases
High speed response at the lowest possible switching
frequency and minimal count of output decoupling
capacitors
Minimized thermal switching losses due to lower
frequency operation
High accuracy load line regulation
High current output by supporting 2−phase operation
Reduced output ripple due to multiphase ripple
cancellation
High power conversion efficiency with heavy and light
loads
Increased immunity from noise introduced by PC board
layout constraints
Ease of use due to independent component selection
Flexibility in design by allowing optimization for either
low cost or high performance
Number of Phases
The number of operational phases can be set by the user.
Tying the SP pin to the VCC pin forces the chip into
single−phase operation. Otherwise, dual−phase operation is
automatically selected, and the chip switches between
single− and dual−phase modes as the load changes to
optimize power conversion efficiency.
In dual−phase configuration, SP is low and the timing
relationship between the two phases is determined by
internal circuitry that monitors the PWM outputs. Because
each phase is monitored independently, operation
approaching 100% duty cycle is possible. In addition, more
than one output can be active at a time, permitting
overlapping phases.
Operation Modes
The number of phases can be static (see the Number of
Phases section) or dynamically controlled by system signals
to optimize the power conversion efficiency with heavy and
light loads.
If SP is set low (user−selected dual−phase mode) during
a VID transient or with a heavy load condition (indicated by
DPRSLP being low and PSI being high), the ADP3208D
runs in 2−phase, interleaved PWM mode to achieve minimal
VCORE output voltage ripple and the best transient
performance possible. If the load becomes light (indicated by
PSI being low or DPRSLP being high), ADP3208D switches
to single−phase mode to maximize the power conversion
efficiency.
In addition to changing the number of phases, the
ADP3208D is also capable of dynamically changing the
control method. In dual−phase operation, the ADP3208D
runs in PWM mode, where the switching frequency is
controlled by the master clock. In single−phase operation
(commanded by the PSI low state), the ADP3208D runs in
RPM mode, where the switching frequency is controlled by
the ripple voltage appearing on the COMP pin. In RPM
mode, the DRVH1 pin is driven high each time the COMP
pin voltage rises to a voltage limit set by the VID voltage and
an external resistor connected from the RPM to GND. If the
device is in single−phase mode and the system signal
DPRSLP is asserted high during the deeper sleep mode of
CPU operation, the ADP3208D continues running in RPM
mode but offers the option of turning off the low−side
(synchronous rectifier) MOSFET when the inductor current
drops to 0. Turning off the low−side MOSFETs at the zero
current crossing prevents reversed inductor current build up
and breaks synchronous operation of high− and low−side
switches. Due to the asynchronous operation, the switching
frequency becomes slower as the load current decreases,
resulting in good power conversion efficiency with very
light loads.
Table 1 summarizes how the ADP3208D dynamically
changes the number of active phases and transitions the
operation mode based on system signals and operating
conditions.
Table 1. Phase Number and Operation Modes
PSI
DPRSLP
VID Transient
(Note 1)
Current Limit
No. of Phases
Selected by User
No. of Phases
in Operation
Operation Mode (Note 2)
*
*
Yes
*
N [2 or 1]
N
PWM, CCM only
1
0
No
*
N [2 or 1]
N
PWM, CCM only
0
0
No
No
*
1
RPM, CCM only
0
0
No
Yes
*
1
PWM, CCM only
*
1
No
No
*
1
RPM, automatic CCM/DCM
*
1
No
Yes
*
1
PWM, CCM only
* = Don’t Care
1. VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient
period is the same as that of PWRGD masking time.
2. CCM stands for continuous current mode, and DCM stands for discontinuous current mode.


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