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ADP3207C Datasheet(PDF) 26 Page - ON Semiconductor

Part No. ADP3207C
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADP3207C Datasheet(HTML) 26 Page - ON Semiconductor

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ADP3207C
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26
Knowing the maximum output thermal current and the
maximum allowed power dissipation, users can find the
required RDS(on) for the MOSFET. For 8−lead SOIC or
8−lead SOIC−compatible packaged MOSFETs the junction
to ambient (PCB) thermal impedance is 50
°C/W. In the worst
case, the PCB temperature is 90
°C during heavy load
operation of the notebook; a safe limit for PSF is 0.6 W at
120
°C junction temperature. Therefore, for this example
(32 A maximum thermal current), RDS(SF) (per MOSFET) is
less than 9.6 m
W for two pieces of low−side MOSFET. This
RDS(SF) is also at a junction temperature of about 120°C;
therefore, the RDS(SF) (per MOSFET) should be lower than
6.8 m
W at room temperature, giving 9.6 mW at high
temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio of
feedback to input needs to be small (less than 10% is
recommended) to prevent accidental turn−on of the
synchronous MOSFETs when the switch node goes high.
The high−side (main) MOSFET has to be able to handle
two main power dissipation components, conduction and
switching losses. The switching loss is related to the amount
of time it takes for the main MOSFET to turn on and off and
to the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, Equation 16
provides an approximate value for the switching loss per main
MOSFETs.
PS(MF) + 2 fSW
VCC IO
nMF
RG
nMF
n
CISS
(eq. 16)
Where:
nMF is the total number of main MOSFETs. RG is the total
gate resistance (1.5
W for the ADP3611 and about 0.5 W for
two pieces of typical high speed switching MOSFETs,
making RG = 2 W). CISS is the input capacitance of the main
MOSFET. The best thing to reduce switching loss is to use
lower gate capacitance devices.
The conduction loss of the main MOSFET is given by:
PC(MF) + D
IO
nMF
2
) 1
12
n
IR
nMF
2
RDS(MF)
(eq. 17)
Where: RDS(MF) is the on−resistance of the MOSFET.
Typically, for main MOSFETs, users want the highest
speed (low CISS) device, but these usually have higher
on−resistance. Users must select a device that meets the total
power dissipation (0.6 W for a single 8−lead SOIC) when
combining the switching and conduction losses.
For example, using an IRF7821 device as the main
MOSFET (four in total; that is, nMF = 4), with about
CISS = 1010 pF (maximum) and RDS(MF) = 18 mW
(maximum at TJ = 120°C) and an IR7832 device as the
synchronous MOSFET (four in total; that is, nSF = 4),
RDS(SF) = 6.7 mW (maximum at TJ = 120°C). Solving for the
power dissipation per MOSFET at IO = 32 A and IR = 10.7 A
yields 420 mW for each synchronous MOSFET and
410 mW for each main MOSFET.
One last consideration is the power dissipation in the
driver for each phase. This is best described in terms of the
QG for the MOSFETs and is given by:
PDRV +
fSW
2
n
nMF QGMF ) nSF QQSF ) ICC
(eq. 18)
VCC
Where:
QGMF is the total gate charge for each main MOSFET.
QGSF is the total gate charge for each synchronous
MOSFET.
This also shows the standby dissipation (ICC x VCC) of the
driver. For the ADP3611, the maximum dissipation should be
less than 300 mW, considering its thermal impedance is
220
°C/W, and the maximum temperature increase is 50°C.
For this example, with ICC = 2 mA, QGMF = 14 nC, and
QGSF = 51 nC, there is 120 mW dissipation in each driver,
which is below the 300 mW dissipation limit. Refer to data
sheet ADP3611 for more details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
and transient response. Use this equation to determine a
starting value:
RR +
AR L
3
AD RDS CR
RR +
0.5
360 nH
3
5
5.2 mW
5pF
+ 462 kW
(eq. 19)
Where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low−side MOSFET on−resistance,
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 20). For stability and noise
immunity, keep this ramp size larger than 0.5 V. In addition,
larger ramp size helps to reduce output voltage ringing back
during step load transient, where EPWM is triggered. Taking
these into consideration, the value of RR is selected as 200 kW.
The internal ramp voltage magnitude can be calculated by:
VR +
AR (1 * D) VVID
RR CR fSW
VR +
0.2
(1 * 0.061)
1.150 V
200 kW
5pF
280 kHz
+ 0.77 V
(eq. 20)
The size of the internal ramp can be made larger or
smaller. If it is made larger, then stability and transient
response improves, but thermal balance degrades. Likewise,
if the ramp is made smaller, then thermal balance improves
at the sacrifice of transient response and stability. The factor
of three in the denominator of Equation 19 sets a minimum


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