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ADP3207C Datasheet(PDF) 18 Page - ON Semiconductor

Part No. ADP3207C
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADP3207C Datasheet(HTML) 18 Page - ON Semiconductor

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ADP3207C
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18
An inherent per phase current limit protects individual
phases in case one or more phases stop functioning because
of a faulty component. This limit is based on the maximum
normal−mode COMP voltage.
After 9 ms in current limit, the ADP3207C will latchoff.
The latchoff can be reset by removing and reapplying VCC,
or by recycling the EN pin low and high for a short time.
The latchoff can be reset by removing and reapplying VCC,
or by recycling the EN pin low and high for a short time.
Changing VID OTF
The ADP3207C is designed to track dynamically
changing VID code. As a result, the converter output
voltage, that is, the CPU VCC voltage, can change without
the need to reset either the controller or the CPU. This
concept is commonly referred to as VID OTF transient. A
VID OTF can occur either under light load or heavy load
conditions. The processor signals the controller by changing
the VID inputs in LSB incremental steps from the start code
to the finish code. The change can be either upwards or
downwards steps.
When a VID input changes state, the ADP3207C detects
the change but ignores the new code for a minimum of
400 ns. This keep out is required to prevent reaction to false
code that can occur by a skew in the VID code while the
7−bit VID input code is in transition. Additionally, the VID
change triggers a PWRGD masking timer to prevent a
PWRGD failure. Each VID change resets and retriggers the
internal PWRGD masking timer. As listed in Table 2, during
any VID transient, the ADP3207C forces a multi−phase
PWM mode regardless of system input signals.
Output Crowbar
To protect the CPU load and output components of the
converter, the PWM outputs are driven low, and DCM and
OD are driven high (that is, commanded to turn on the
low−side MOSFETs of all phases) when the output voltage
exceeds an OVP threshold of 1.7 V as specified by IMVP−6.
Turning on the low−side MOSFETs discharges the output
capacitor as soon as reverse current builds up in the
inductors. If the output overvoltage is due to a short of the
high−side MOSFET, then this crowbar action current limits
the input supply or causes the input rail fuse to blow,
protecting the microprocessor from destruction.
Once Overvoltage Protection (OVP) is triggered, the
ADP3207C is latched off. The latchoff function can be reset
by removing and reapplying VCC, or by recycling EN low
and high for a short time. OVP can be disabled by grounding
the TTSENSE pin. The OVP comparator monitors the
output voltage via the CSREF pin.
Reverse Voltage Protection
Very large reverse currents in inductors can cause
negative VCore voltage, which is harmful to the CPU and
other output components. ADP3207C provides Reverse
Voltage Protection (RVP) function without additional
system cost. The VCore voltage is monitored through the
CSREF pin. Any time the CSREF pin voltage is below
−300 mV, the ADP3207C triggers its RVP function by
disabling all PWM outputs and setting both the DCM and
OD pins low. Thus, all the MOSFETs are turned off. The
reverse inductor current can be quickly reset to 0 by
dumping the energy built up in the inductor into the input dc
voltage source via the forward biased body diode of the
high−side MOSFETs. The RVP function is terminated when
the CSREF pin voltage returns above −100 mV.
Occasionally, overvoltage crowbar protection results in
negative VCore voltage, because turn−on of all low−side
MOSFETs leads to very large reverse inductor current. To
prevent damage of the CPU by negative voltage, ADP3207C
keeps its RVP monitoring function alive even after OVP
latchoff. During OVP latchoff, if the CSREF pin voltage
drops below −300mV, then all low−side MOSFETs are
turned off by setting both DCM and OD low. The DCM pin
and the OD pin are set high again when CSREF voltage
recovers above −100 mV.
Output Enable and UVLO
The VCC supply voltage to the controller must be higher
than the UVLO upper threshold, and the EN pin must be
higher than its logic threshold so the ADP3207C can begin
switching. If the VCC voltage is less than the UVLO
threshold, or the EN pin is logic low, then the ADP3207C is
in shutdown. In shutdown, the controller holds the PWM
outputs at ground, shorts the SS pin capacitor to ground, and
drives DCM and OD pins low.
Proper power supply sequencing during startup and
shutdown of the ADP3207C must be adhered to. All input
pins must be at ground prior to applying or removing VCC.
All output pins should be left in high impedance state while
VCC is off.
Thermal Throttling Control
The ADP3207C includes a thermal monitoring circuit to
detect if the temperature of the variable resistor (VR) has
exceeded a user−defined thermal throttling threshold. The
thermal monitoring circuit requires an external resistor
divider connected between the VCC pin and GND. The
divider consists of an NTC thermistor and a resistor. To
generate a voltage that is proportional to temperature, the
midpoint of the divider is connected to the TTSENSE pin.
Whenever the temperature trips the set alarm threshold, an
internal comparator circuit compares the TTSENSE voltage
to a half VCC threshold and outputs a logic level signal at the
VRTT output. The VRTT output is designed to drive an
external transistor that, in turn, provides the high current,
open drain VRTT signal that is required by the IMVP−6
specification. When the temperature is around the set alarm
point, the internal VRTT comparator has a hysteresis of about
100 mV to prevent high frequency oscillation of VRTT. The
TTSENSE pin also serves the function of disabling OVP. In
extreme heat, users should make sure that the TTSENSE pin
voltage remains above 1.0 V if OVP is desired.


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