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ADP3207C Datasheet(PDF) 17 Page - ON Semiconductor

Part No. ADP3207C
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADP3207C Datasheet(HTML) 17 Page - ON Semiconductor

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code to an analog reference voltage. During startup, the DAC
ignores the VID code. The internal DAC steps through each
VID code from 0 V to the boot voltage. The DAC steps to the
next VID code every 16
ms. With 12.5 mV difference between
VID codes, the soft−start slew rate is 12.5 mV / 16
ms or
approximately 0.78 mV/
ms. This gives a soft−start time of
approximately 1.5 ms.
After the DAC reaches the boot voltage, an internal 100
timer starts. This is the 100
ms boot time. After the boot time
is over, the CLKEN is asserted low. The DAC then reads the
VID code. There is a soft transition from the boot voltage to
the VID voltage. After CLKEN is asserted low, these is an
internal 8 ms timer that asserts PWRGD high. The whole
powerup sequence, including soft−start, is illustrated in
Figure 26.
In VCC UVLO or in shutdown, PWM1, PWM2, and
PWM3 are pulled low. When VCC ramps above the upper
UVLO threshold and EN is asserted high, the ADP3207C
enables internal bias and starts a reset cycle that lasts about
ms to 60 ms. Next, when initial reset is over, the chip detects
the number of phases set by the user and gives a go signal to
start the internal soft−start. After the CLKEN is asserted low,
the ADP3207C reads the VID codes provided by the CPU on
VID0 to VID6 input pins. The VCore voltage changes from
VBOOT to the VID voltage by a well−controlled soft
transition, as introduced in the Soft Transient section.
The PWRGD signal is not asserted until there is a
tCPU_PWRGD delay of approximately 8 ms, which is fixed
internally by the ADP3207C.
If either EN is taken low or VCC drops below the lower VCC
UVLO threshold, the PWM1, PWM2, and PWM3 signals
stop switching. An internal MOSFET discharges the output
voltage through the CSREF pin. The internal CSREF
MOSFET has a resistance of approximately 100
Figure 26. Powerup Sequence
tPWRGD Delay
Soft Transient
The ADP3207C provides a soft transient function to
reduce inrush current during various transitions, including
the entrance/exit of deeper sleep and the transition from
VBOOT to VID voltage. Reducing the inrush current helps
decrease the acoustic noise generated by the MLCC input
capacitors and inductors.
The soft transient feature is implemented internally. When
the ADP3207C detects a new VID code, the DAC steps
through each VID code until is reaches the final code. For a
fast slew rate, the ADP3207C steps to the next VID code
every 1
ms. This gives a fast slew rate of 12.5 mV/ms. For a
slow slew rate, the ADP3207C steps to the next VID code
every 4
ms. This gives a slew rate of 3.125 mV/ms.
With DPRSLP asserted high, the slow slew rate is enabled.
With DPRSLP asserted low, the fast slew rate is enabled.
Table 2 summarizes the soft transient slew rate.
Table 2. Soft Transient Slew Rate
VID Transient
Slew Rate
Fast Exit from Deeper Sleep
+12.5 mV/ms
Slow Exit from Deeper Sleep
+3.125 mV/ms
Transient from VBOOT to VID
(Note 1)
$3.125 mV/ms
1. DNC = Do Not Care.
Current Limit
The ADP3207C compares the differential output of a
current sense amplifier to a programmable current limit
setpoint to provide current limiting function. The current limit
set point is set with a resistor connected from ILIM pin to
CSCOMP pin. This is the Rlim resistor. During normal
operation, the voltage on the ILIM pin is equal to the CSREF
pin. The voltage across Rlim is equal to the voltage across the
current sense amplifier (from CSREF pin to CSCOMP pin).
This voltage is proportional to output current. The current
through Rlim is proportional to the output inductor current.
The current through Rlim is compared with an internal
reference current. When the Rlim current goes above the
internal reference current, the ADP3207C goes into current
limit. The current limit circuit is shown in Figure 11.
Figure 27. Current Limit Circuit
20 mA
During startup when the output voltage is below 200 mV, a
secondary current limit is activated. This is necessary because
the voltage swing on CSCOMP cannot extend below ground.
The secondary current limit circuit clamps the internal COMP
voltage and sets the internal compensation ramp termination
voltage at 1.5 V level. The clamp actually limits voltage drop
across the low side MOSFETs through the current balance

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