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ADP3207C Datasheet(PDF) 5 Page - ON Semiconductor

Part No. ADP3207C
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADP3207C Datasheet(HTML) 5 Page - ON Semiconductor

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ADP3207C
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V,
DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = −10°C to 100°C, unless otherwise noted (Note 1). RREF = 80 kW.
Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)
FB, LLINE Voltage Range
(Note 2)
VFB, VLLINE
Relative to CSREF = VDAC
−200
+200
mV
FB, LLINE Offset Voltage
(Note 2)
VOSVEA
Relative to CSREF = VDAC
−0.5
+0.5
mV
FB Bias Current (Note 2)
IFB
−1.0
1.0
A
LLINE Bias Current (Note 2)
ILL
−50
50
nA
LLINE Positioning Accuracy
VFB − VVID
Measured on FB relative to VVID, LLINE
forced 80 mV below CSREF
−78
−80
−82
mV
COMP Voltage Range
VCOMP
Operating Range
0.85
4.0
V
COMP Current
ICOMP
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
0.75
6.0
mA
COMP Slew Rate
SRCOMP
CCOMP = 10 pF, CSREF = VDAC, Open loop
configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
15
−20
V/ms
Gain Bandwidth (Note 2)
GBW
Non−inverting unit gain configuration,
RFB = 1 kW
20
MHz
VID DAC VOLTAGE REFERENCE
VDAC Voltage Range
See VID Code Table
0
1.5
V
VDAC Accuracy
VFB − VVID
Measured on FB (includes offset), relative to
VVID, for VID table see Table 3,
TA = −10°C to 85°C
VVID = 1.2125 V to 1.5000 V
VVID = 0.3000 V to 1.2000 V
−9.0
−7.0
+9.0
+7.0
mV
VDAC Differential Non−linearity (Note 2)
−1.0
+1.0
LSB
VDAC Line Regulation
DVFB
VCC = 4.75 V to 5.25 V
0.05
%
VDAC Boot Voltage
VBOOTFB
Measured during boot delay period
1.200
V
Soft−Start Delay (Note 2)
tDSS
Measured from EN pos edge to FB = 50 mV
200
ms
Soft−Start Time
tSS
Measured from EN pos edge to FB settles to
VBOOT = 1.2 V within −5%
ADP3207C
ADP3207CF
1.4
0.14
ms
Boot Delay
tBOOT
Measured from FB settling to VBOOT = 1.2 V
within −5% to CLKEN neg edge
100
ms
VDAC Slew Rate
Soft−Start ADP3207C
Soft−Start ADP3207CF
Non−LSB VID step, DPRSLP = H, Slow C4
Entry/Exit
Non−LSB VID step, DPRSLP = L, Fast C4
Exit
0.0625
0.625
0.25
1.0
LSB/
ms
FBRTN Current
IFBRTN
90
200
mA
VOLTAGE MONITORING AND PROTECTION − Power Good
CSREF Undervoltage
Threshold
VUVCSREF
Relative to nominal DAC Voltage:
= 0.5125 V to 1.5 V
= 0.3 V to 0.5 V
−240
−160
−300
−300
−360
−360
mV
CSREF Overvoltage
Threshold
VOVCSREF
Relative to nominal DAC Voltage
150
200
250
mV
CSREF Crowbar Voltage
Threshold
VCBCSREF
Relative to FBRTN
1.65
1.7
1.75
V
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.


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