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ADM1032ARZ Datasheet(PDF) 8 Page - ON Semiconductor

Part No. ADM1032ARZ
Description  ±1℃ Remote and Local System Temperature Monitor
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADM1032ARZ Datasheet(HTML) 8 Page - ON Semiconductor

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Temperature Data Format
One LSB of the ADC corresponds to 0.125
°C, so the ADC
can measure from 0
°C to 127.875°C. The temperature data
format is shown in Table 1 and Table 2.
The results of the local and remote temperature
measurements are stored in the local and remote temperature
value registers and are compared with limits programmed
into the local and remote high and low limit registers.
Table 1. Temperature Data Format (Local
Temperature and Remote Temperature High Byte
Digital Output
0 000 0000
0 000 0001
0 000 1010
0 001 1001
0 011 0010
0 100 1011
0 110 0100
0 111 1101
0 111 1111
Table 2. Extended Temperature Resolution (Remote
Temperature Low Byte
Extended Resolution
Remote Temperature Low Byte
0 000 0000
0 010 0000
0 100 0000
0 110 0000
1 000 0000
1 010 0000
1 100 0000
1 110 0000
ADM1032 Registers
The ADM1032 contains registers that are used to store the
results of remote and local temperature measurements and
high and low temperature limits and to configure and control
the device. A description of these registers follows, and
further details are given in Table 3 to Table 7.
Address Pointer Register
The address pointer register itself does not have, or
require, an address because it is the register the first data byte
of every write operation is written to automatically. This
data byte is an address pointer that sets up one of the other
registers for the second byte of the write operation or for a
subsequent read operation.
The power−on default value of the address pointer register
is 00h. Therefore, if a read operation is performed
immediately after power−on without first writing to the
address pointer, the value of the local temperature is returned
because its register address is 00h.
Value Registers
The ADM1032 has three registers to store the results of
local and remote temperature measurements. These
registers are written to by the ADC only and can be read over
the SMBus.
Offset Register
Series resistance on the D+ and D− lines in processor
packages and clock noise can introduce offset errors into the
remote temperature measurement. To achieve the specified
accuracy on this channel, these offsets must be removed.
The offset value is stored as an 11−bit, twos complement
value in Register 11h (high byte) and Register 12h (low byte,
left justified). The value of the offset is negative if the MSB
of Register 11h is 1 and positive if the MSB of Register 12h
is 0. The value is added to the measured value of the remote
The offset register powers up with a default value of 0
and has no effect if nothing is written to them.
Table 3. Sample Offset Register Codes
Offset Value
1 111 1100
0 000 0000
1 111 1111
0 000 0000
1 111 1111
1 110 0000
0 000 0000
0 000 0000
0 000 0000
0 010 0000
0 000 0001
0 000 0000
0 000 0100
0 000 0000
Status Register
Bit 7 of the status register indicates that the ADC is busy
converting when it is high. Bit 6 to Bit 3, Bit 1, and Bit 0 are
flags that indicate the results of the limit comparisons. Bit 2
is set when the remote sensor is open circuit.
If the local and/or remote temperature measurement is
above the corresponding high temperature limit, or below or
equal to the corresponding low temperature limit, one or
more of these flags is set. These five flags (Bit 6 to Bit 2) are
NOR’ed together, so that if any of them are high, the ALERT
interrupt latch is set and the ALERT output goes low.
Reading the status register clears the five flag bits, provided
that the error conditions that caused the flags to be set have
gone away. While a limit comparator is tripped due to a value
register containing an out−of−limit measurement, or the
sensor is open circuit, the corresponding flag bit cannot be
reset. A flag bit can only be reset if the corresponding value
register contains an in−limit measurement or the sensor is
The ALERT interrupt latch is not reset by reading the
status register but is reset when the ALERT output is
serviced by the master reading the device address, provided
the error condition has gone away and the status register flag
bits are reset.

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