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ADM1025 Datasheet(PDF) 16 Page - ON Semiconductor
ONSEMI [ON Semiconductor]
ADM1025 Datasheet(HTML) 16 Page - ON Semiconductor
/ 21 page
Preliminary Technical Data
Rev. P5 | Page 16 of 21| www.onsemi.com
The device whose INT output is low responds to the Alert
Response Address, and the master reads its device address.
The address of the device is now known and it can be
interrogated in the usual way.
If more than one device’s INT output is low, the one with
the lowest device address will have priority, in accordance
with normal SMBus arbitration.
Once the ADM1025/ADM1025A has responded to the
Alert Response Address, it will reset its INT output;
however, if the error condition that caused the interrupt
persists, INT will be reasserted on the next monitoring
NAND TREE TESTS
A NAND tree is provided in the ADM1025/ADM1025A for
Automated Test Equipment (ATE) board level connectivity
testing. The device is placed into NAND Test Mode by
powering up with Pin 9 (D-/NTI) held high. This pin is
automatically sampled after power-up, and if it is connected
high, the NAND test mode is invoked.
In NAND test mode, all digital inputs may be tested as
illustrated below. ADD/RST/INT/NTO will become the NAND
test output pin.
To perform a NAND tree test, all pins are initially driven low.
The test vectors set all inputs low, then one-by-one toggle them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the
output of the tree, cycling toward the farthest, causes the output
of the tree to toggle with each input change. Allow for a typical
propagation delay of 500 ns. The structure of the NAND tree is
shown in Figure 18.
Figure 18. NAND Tree
Note: If any of the inputs shown in Figure 18 are unused, they
should not be connected directly to ground but via a resistor
such as 10 kΩ. This will allow the ATE to drive every input high
so that the NAND tree test can be properly carried out. Refer to
Table 19 for Test Vectors.
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