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ADM1025 Datasheet(PDF) 15 Page - ON Semiconductor
ONSEMI [ON Semiconductor]
ADM1025 Datasheet(HTML) 15 Page - ON Semiconductor
/ 21 page
Preliminary Technical Data
Rev. P5 | Page 15 of 21| www.onsemi.com
As the resistors will form part of the input attenuators, they will
affect the accuracy of the analog measurement if their value is
too high. The analog input channels are calibrated assuming an
external series resistor of 500 Ω, and the accuracy will remain
within specification for any value from zero to 1 kΩ, so a
standard 510 Ω resistor is suitable.
The worst such accident would be connecting 0 V to 12 V—a
total of 12 V difference. With the series resistors, this would
draw a maximum current of approximately 12 mA.
LAYOUT AND GROUNDING
Analog inputs will provide best accuracy when referred to a
clean ground. A separate, low impedance ground plane for
analog ground, which provides a ground point for the voltage
dividers and analog components, will provide best performance
but is not mandatory.
The power supply bypass, the parallel combination of 10 μF
(electrolytic or tantalum) and 0.1 μF (ceramic) bypass
capacitors connected between Pin 9 and ground, should also be
located as close as possible to the ADM1025/ADM1025A.
As previously mentioned, Pin 16 is a multifunction pin. Its state
after power-on is latched to set the lowest two bits of the serial
bus address. During NAND tree board-level connectivity
testing, it functions as the output of the NAND tree. It may also
be used as a reset output, or as an interrupt output for out-of-
limit temperature/voltage events.
Pin 16 is programmed as a reset output by clearing Bit 0 of the
Test Register and setting Bit 7 of the VID Register. A low going,
20 ms, reset output pulse can then be generated by setting Bit 4
of the Configuration Register.
If Bit 7 of the VID Register is cleared, Pin 16 can be programmed
as an interrupt output for out-of-limit temperature/voltage
events (INT). Desired interrupt operation is achieved by
changing the values of Bits 1 and 0 of the Test Register as shown
in Table 7. Note, however, that Bits 2 to 7 of the Test Register
must be zeros (not don’t cares). If, for example, INT is
programmed for thermal and voltage interrupts, then if any
temperature or voltage measurement goes outside its respective
high or low limit, the INT output will go low. It will remain low
until Status Register 1 is read, when it will be cleared. If the
temperature or voltage remains out of limit, INT will be
reasserted on the next monitoring cycle. INT can also be
cleared by issuing an Alert Response Address Call.
Table 7. Controlling the Operation of INT
Thermal Interrupt Only
Voltage Interrupt Only
Voltage and Thermal Interrupts
Note that Bit 7 of VID register should be zero, and that Bits 2 to
7 of Test Register must be zeros.
When Pin 16 is used as a RST or INT output, it is open-drain
and requires an external pull-up resistor. This will restrict the
address function on Pin 16 to being high at power-up. If the
RST or INT function is required and two ADM1025/
ADM1025As are to be used on the same serial bus, A1/A0 can
be set to 10 by using a high value pull-up on Pin 16 (100 kΩ or
greater). This will not override the “floating” condition of ADD
Note, however, that the RST/INT outputs of two or more
devices cannot be wire-OR’d, since the devices would then have
the same address. If the RST/INT outputs need to be connected
to a common interrupt line, they can be OR’d together using the
circuit of Figure 17.
If the RSTor INT functionality is not required, a third address
may be used by setting A1/A0 to 00 by using a 1 kΩ pull-down
resistor on Pin 16. Note that this address should not be used if
RSTor INT is required, since using this address will cause the
device to appear to be generating resets or interrupts, since
Pin 16 will be permanently tied low.
Figure 17. Using Two ADM1025/ADM1025As on the Same Bus with a
GENTERATING AN SMBALERT
The INT output can be used as an interrupt output or can be
used as an SMBALERT. One or more INT outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s INT line goes low, the following procedure
SMBALERTis pulled low.
Master initiates a read operation and sends the Alert
Response Address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
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