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74HC138DR2G Datasheet(PDF) 5 Page - ON Semiconductor

Part No. 74HC138DR2G
Description  1−of−8 Decoder/ Demultiplexer High−Performance Silicon−Gate CMOS
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

74HC138DR2G Datasheet(HTML) 5 Page - ON Semiconductor

  74HC138DR2G Datasheet HTML 1Page - ON Semiconductor 74HC138DR2G Datasheet HTML 2Page - ON Semiconductor 74HC138DR2G Datasheet HTML 3Page - ON Semiconductor 74HC138DR2G Datasheet HTML 4Page - ON Semiconductor 74HC138DR2G Datasheet HTML 5Page - ON Semiconductor 74HC138DR2G Datasheet HTML 6Page - ON Semiconductor 74HC138DR2G Datasheet HTML 7Page - ON Semiconductor 74HC138DR2G Datasheet HTML 8Page - ON Semiconductor 74HC138DR2G Datasheet HTML 9Page - ON Semiconductor  
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74HC138
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5
Figure 1.
50%
tPHL
tPLH
VCC
GND
Figure 2.
VALID
VALID
OUTPUT Y
50%
tf
tr
VCC
GND
tPLH
tTLH
90%
50%
10%
OUTPUT Y
INPUT CS1
tPHL
90%
50%
10%
tTHL
INPUT A
SWITCHING WAVEFORMS
tTHL
tTLH
VCC
GND
tr
tPHL
tPLH
OUTPUT Y
INPUT
CS2, CS3
90%
50%
10%
90%
50%
10%
Figure 3.
tf
*Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active−low.
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.
OUTPUTS
Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Active−low Decoded outputs. These outputs assume a
low level when addressed and the chip is selected. These
outputs remain high when not addressed or the chip is not
selected.


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