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PCA9534ADGVRG4 Datasheet(PDF) 9 Page - Texas Instruments |
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PCA9534ADGVRG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 39 page SCL Start Condition Data 1 Valid SDA Write to Port Data Out From Port R/W ACK From Slave ACK From Slave ACK From Slave 1 9 8 7 6 5 4 3 2 Data 1 1 A2 0 1 S 1 1 A1 A0 0 A 0 0 0 0 0 0 0 A A P tpv Data to Port Command Byte Slave Address Data 1/0 A2 0 1 S 1 1 A1 A0 0 A 1 0 0 0 0 0 0 A A P SCL SDA Data to Register Start Condition R/W ACK From Slave ACK From Slave ACK From Slave 1 9 8 7 6 5 4 3 2 Data to Register Command Byte Slave Address PCA9534A www.ti.com SCPS141F – SEPTEMBER 2006 – REVISED JUNE 2010 Interrupt Output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1 or vice versa. The INT output has an open-drain structure and requires pullup resistor to VCC. Bus Transactions Data is exchanged between the master and PCA9534A through write and read commands. Writes Data is transmitted to the PCA9534A by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on the number of data bytes sent in one write transmission. Figure 6. Write to Output Port Register <br/> Figure 7. Write to Configuration or Polarity Inversion Registers Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): PCA9534A |
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