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PCA9534ADGVR Datasheet(PDF) 5 Page - Texas Instruments |
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PCA9534ADGVR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 39 page Data From Shift Register Data From Shift Register Write Configuration Pulse Write Pulse Read Pulse Write Polarity Pulse Data From Shift Register Output Port Register Configuration Register Input Port Register Polarity Inversion Register Polarity Register Data Input Port Register Data GND ESD Protection Diode P0 to P7 VCC Output Port Register Data Q1 Q2 D CK FF Q Q D CK FF Q Q D CK FF Q Q D CK FF Q Q To INT PCA9534A www.ti.com SCPS141F – SEPTEMBER 2006 – REVISED JUNE 2010 SIMPLIFIED SCHEMATIC OF P0 TO P7 A. At power-on reset, all registers return to default values. I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. I 2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the start and the stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see Figure 2). Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): PCA9534A |
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