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EPF8452A Datasheet(PDF) 1 Page - Altera Corporation |
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EPF8452A Datasheet(HTML) 1 Page - Altera Corporation |
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1 / 62 page  ® Altera Corporation 1 FLEX 8000 Programmable Logic Device Family January 2003, ver. 11.1 Data Sheet DS-F8000-11.1 3 1 Features... ■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) – 2,500 to 16,000 usable gates – 282 to 1,500 registers ■ System-level features – In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices –MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels – Low power consumption (typical specification is 0.5 mA or less in standby mode) ■ Flexible interconnect –FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state nets ■ Powerful I/O pins ■ Programmable output slew-rate control reduces switching noise Table 1. FLEX 8000 Device Features Feature EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A Usable gates 2,500 4,000 6,000 8,000 12,000 16,000 Flipflops 282 452 636 820 1,188 1,500 Logic array blocks (LABs) 26 42 63 84 126 162 Logic elements (LEs) 208 336 504 672 1,008 1,296 Maximum user I/O pins 78 120 136 152 184 208 |
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