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C8051F711-GQ Datasheet(PDF) 6 Page - Silicon Laboratories |
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C8051F711-GQ Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 290 page C8051F70x/71x 6 Rev. 0.3 26.5. Port Match ..................................................................................................... 175 26.6. Special Function Registers for Accessing and Configuring Port I/O ............. 177 27. Cyclic Redundancy Check Unit (CRC0)............................................................. 193 27.1. 16-bit CRC Algorithm..................................................................................... 194 27.2. 32-bit CRC Algorithm..................................................................................... 195 27.3. Preparing for a CRC Calculation ................................................................... 196 27.4. Performing a CRC Calculation ...................................................................... 196 27.5. Accessing the CRC0 Result .......................................................................... 196 27.6. CRC0 Bit Reverse Feature............................................................................ 199 28. SMBus................................................................................................................... 201 28.1. Supporting Documents .................................................................................. 202 28.2. SMBus Configuration..................................................................................... 202 28.3. SMBus Operation .......................................................................................... 202 28.3.1. Transmitter Vs. Receiver....................................................................... 203 28.3.2. Arbitration.............................................................................................. 203 28.3.3. Clock Low Extension............................................................................. 203 28.3.4. SCL Low Timeout.................................................................................. 203 28.3.5. SCL High (SMBus Free) Timeout ......................................................... 204 28.4. Using the SMBus........................................................................................... 204 28.4.1. SMBus Configuration Register.............................................................. 204 28.4.2. SMB0CN Control Register .................................................................... 208 28.4.2.1. Software ACK Generation ............................................................ 208 28.4.2.2. Hardware ACK Generation ........................................................... 208 28.4.3. Hardware Slave Address Recognition .................................................. 210 28.4.4. Data Register ........................................................................................ 213 28.5. SMBus Transfer Modes................................................................................. 214 28.5.1. Write Sequence (Master) ...................................................................... 214 28.5.2. Read Sequence (Master) ...................................................................... 215 28.5.3. Write Sequence (Slave) ........................................................................ 216 28.5.4. Read Sequence (Slave) ........................................................................ 217 28.6. SMBus Status Decoding................................................................................ 217 29. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 223 29.1. Signal Descriptions........................................................................................ 224 29.1.1. Master Out, Slave In (MOSI)................................................................. 224 29.1.2. Master In, Slave Out (MISO)................................................................. 224 29.1.3. Serial Clock (SCK) ................................................................................ 224 29.1.4. Slave Select (NSS) ............................................................................... 224 29.2. SPI0 Master Mode Operation ........................................................................ 225 29.3. SPI0 Slave Mode Operation .......................................................................... 226 29.4. SPI0 Interrupt Sources .................................................................................. 227 29.5. Serial Clock Phase and Polarity .................................................................... 227 29.6. SPI Special Function Registers ..................................................................... 229 30. UART0 ................................................................................................................... 236 30.1. Enhanced Baud Rate Generation.................................................................. 237 30.2. Operational Modes ........................................................................................ 238 |
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