DS32ELX0124 datasheet(3/28 Pages) NSC

Part #	DS32ELX0124

Description	125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

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Manufacturer	NSC [National Semiconductor (TI)]

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Pin Descriptions

Pin Name

Pin Number

I/O, Type

Description

VDD33

1, 15, 18, 36

I, VDD

3.3V supply

VDD25

7, 25, 35

I, VDD

2.5V supply

VDD_PLL

28

I, VDD

3.3V supply

LF_CP

27

Analog

Loop filter capacitor connection

LF_REF

26

Analog

Loop filter ground reference

Exposed Pad

49

GND

Exposed Pad must be connected to GND by 9 vias.

CML I/O

RxIN0+

RxIN0-

16

17

I, CML

Non-inverting and inverting high speed CML differential inputs of the

deserializer. These inputs are internally terminated.

RxIN1+

RxIN1-

19

20

I, CML

DS32ELX0124 only. Non-inverting and inverting high speed CML

differential inputs of the deserializer. These inputs are internally

terminated.

TxOUT+

TxOUT-

21

22

O, CML

DS32ELX0124 only. Retimed serialized high speed output. Non-inverting

and inverting speed CML differential outputs of the deserializer. These

outputs are internally terminated.

LVDS Parallel Data Bus

RxCLKOUT+

RxCLKOUT-

37

38

O, LVDS

Deserializer output clock. RxCLKOUT+/- are the non-inverting and

inverting LVDS recovered clock output pins.

RxOUT[0:4]+/-

39, 40, 41, 42, 43, 44, 45,

46, 47, 48

O, LVDS

Deserializer output data. RxOUT[0:4]+/- are the non-inverting and

inverting LVDS deserialized output data pins.

3

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Manufacturer	Part #	Datasheet	Description
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DS32ELX0124 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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